FEE Electronics progress Mezzanine layout progress FEE64 progress FEE64 initial testing Test mezzanine. VHDL progress in TBU A few of the remaining tasks 3rd September 2009

Mezzanine Layout Progress Layout complete. Checked :- ASICs can be mounted. Board is manufacturable. Board passes DRC. Check :- Layout and design is acceptable for ASIC and mechanics. 3rd September 2009

FEE64 progress targets September 3rd : September 21st : October 31st : PCB manufactured and shipped to assembler and DL. September 21st : Assembled boards delivered this week. Commissioning commences - PJCS, MK, LM. October 31st : Milestone --- Decision to proceed with experiment. 3rd September 2009

Initial testing of FEE64 Power supplies – 28 : Check for noise, stability, accuracy, efficiency…. FPGA – Check configuration via JTAG. Check processor operates with internal memory and terminal. Check configuration from EEPROM. DDR2 Memory Run test system developed by DSDG. Check results and optimise access speed for best performance. Gbit Ethernet ASIC communications and discriminator output timing Analog buffers and ADCs 3rd September 2009

Test mezzanine The board is to allow the exercising of the FEE64 analog and digital inputs. All active signals will be routed with identical lengths and consideration of type. Target is to produce them by Mid October. 3rd September 2009

Collaboration with Detector Systems Development Group (DSDG) of TBU Collaboration with Detector Systems Development Group (DSDG) of TBU. (Technology Business Unit ) Completed : Gbit data rate from memory on the devkit => 240Mbit/sec . System boots with fallback to golden copy. Created a DMA peripheral with transfer rate of 1.1Gbytes/sec. Pin allocation of FEE64 memory and Gbit signals checked. Create a memory test and configuration system. Review the FEE64 schematic and pcb layout Next steps : Commissioning 3rd September 2009

A few of the remaining Tasks Manufacture Mezzanine. Complete Mechanical design. ( Is waiting for final component heights ) Test documentation. Commission first FEE64 units VHDL for first experimental use. Full Linux processor with peripherals and DMA ( from DSDG work ) ASIC communications ( from prototype work ) ASIC multiplexed readout. ( from prototype work ) Timestamped based on discriminator signals. Formatted and transferred to processor memory as four time ordered data streams. FEE64 design documentation. Prepare for production. 3rd September 2009