CS170 Computer Organization and Architecture I Ayman Abdel-Hamid Department of Computer Science Old Dominion University Lecture 10: 9/26/2002 Lecture 10: 9/26/2002 CS170 Fall 2002

Outline Problem 2.15 Rates of Improvement Influences on Performance Summary of performance tests A look ahead (chapter 3) Lecture 10: 9/26/2002 CS170 Fall 2002

Rates of Improvement F = (1 + R)N F improvement factor R rate of improvement per duration (e.g., per year) N number of durations (e.g., number of years) For DRAMs, the component density increases 60% per year. What is the improvement factor in 3 years? R = 0.60 N = 3 F = (1+R)N = (1+0.6)3 = 4.096 Lecture 10: 9/26/2002 CS170 Fall 2002

Influences on Performance Execution time = IC * CPI * Cycle time = IC * [CPU cycles per instruction + Memory cycles per instruction ] * cycle time = IC * [CPU cycles per instruction + (References per instruction * cycles per reference) ] * Cycle time Instruction Set Architecture Compiler Technology CPU Implementation Cache and Memory Hierarchy From “Cache and Memory Hierarchy Design”, S.A. Przybylski Morgan Kaufman Publishers, Inc. 1990 Lecture 10: 9/26/2002 CS170 Fall 2002

Performance Tests Kernels Synthetic Benchmarks Small pieces of real programs, subroutines or inner loops. Examples Livermore (series of 21 small loop fragments) loops and Linpack (portion of a linear algebra subroutine package). Very popular for benchmarking scientific applications. Can overstate performance of real applications Synthetic Benchmarks Whetstone and Dhrystone Small and Simple benchmarks Small and simple codes embodying a single well known algortihm. An example is a Quicksort code. They are too simple and too restricted in operations to test performance. Mixtures of real programs SPEC Lecture 10: 9/26/2002 CS170 Fall 2002

A Look Ahead Chapter 3 Overview of computer organization Fetch/Execute cycle Computer operations addressing modes Instruction set design principles Overview of MIPS architecture Stored program concept Learn a subset of MIPS assembly language Show how MIPS instructions are represented in machine language Contrast MIPS architecture with other (I80X89 and PowerPC architectures Lecture 10: 9/26/2002 CS170 Fall 2002