University of Texas at Austin DATA WORDLENGTH Kyungtae REDUCTION for LOW POWER Han, Brian L. Evans, and Earl E. Swa University of Texas at Austin DSP SOFTWARE rtzlander, Jr

Low-Power at Software Level Portable wireless computing demands minimizing power dissipation Minimizing power consumption Reduce supply voltage Decrease switching activity Software can reduce power consumption Ordering of operation Changing of number representation Reducing of data wordlength Data wordlength reduction (The filled circles affect the switching power consumption)

Objective and Problems Software level power minimization with reducing data wordlength without any hardware modifications Problems How much can shorter data wordlength reduce power consumption? Formulation of power consumption according to reduced data wordlength

Power Consumption Average power consumption Switching power consumption

Multiply Unit for Digital Wireless Transceivers Multiply unit is usually a major source of power consumption in typical DSP applications Multiply unit is required for digital wireless communications Digital filters, equalizers, FFT/IFFT, digital down/up converter, etc. TMS320C5x Power Dissipation Characteristics from www.ti.com

Data Wordlength Reduction Multiplier architecture is unchanged Input data wordlength reduction Signed right shift Move toward the least significant bit (LSB) Arithmetic right shift Truncation Make LSB side to be zero values

Simulation Multiplier Transition Counts Average transition counts of all gate output All gates are assumed to have a unit gate delay Node transitions counted 10,000 random data Discrete Event Simulation: Verilog Compiler Simulator Histogram of Transition Counts

Reduction in Wallace Multiplier Fixed-size Wallace multiplier (32 bits x 32 bits) n2 rate reduction in truncation method TI C64 uses a Wallace tree with 3-2 compressors Average switching activity in 32-bit Wallace multiplier Data wordlength Signed Right Shift Truncation 32 bits 100% 16 bits 130% 28% 8 bits 142% 6% 4 bits 150% 2%

Reduction in Booth Multiplier Fixed-size 32 bit Radix-4 modified Booth multiplier Other TI DSP processors use the Booth architecture Average switching activity in a 32 bit Radix-4 modified Booth multiplier Data wordlength Signed Right Shift Truncation 32 bits 100% 16 bits 85% 42% 8 bits 76% 19% 4 bits 69% 10%

Conclusion and Future Work Reduce power consumption by altering multiplications in software without any hardware modifications Require truncation or signed right shift operation and decrease dynamic range Future work Find optimum wordlength reduction and minimize the additional operations Optimum wordlength Error [1/DR] Power Wordlength (DR: Dynamic Range)