Kyle Fitzpatrick Konstantin Zak 11/29/2004 Makefiles: A Tutorial Kyle Fitzpatrick Konstantin Zak 11/29/2004

Outline Compiling Necessity for Makefiles Components of Makefiles Examples

Compilation Compiler – C to assembly Assembler – Assembly to object code Linker – Links object code with built in functions

Compiling with Multiple Files Compile green.o: cc -c green.c Compile blue.o: cc -c blue.c Link the parts together: cc green.o blue.o

History of Make Original Unix tools for Software Engineering S.I. Feldman of AT&T Bell Labs circa 1975. Public domain versions now, such as GNU

Before Makefiles Use the up arrow to go back to previous compile statement Two major downfalls If compile command is lost, or computers switched, command must be retyped If changes only made to one file, recompiling everything is time consuming and inefficient

Need for Makefiles Large programming projects Compiling multiple files from command line can become tedious GNU Make program makes it much easier Those who have compiled software on Linux probably used ‘make’

How Makefiles Work When ‘make’ is invoked, it looks for a file called ‘Makefile’ Makefile holds a set of rules for compiling a project

Rules A simple makefile consists of "rules" with the following shape: target ... : prerequisites ... command ...

Definitions Target – name of a file that is generated by a program, such as executables or objects Prerequisite – file that is used as input to create the target Usually multiple inputs Command – action that make carries out

Dependencies

Macros Make string substitutions for files or command options that appear a lot form NAME=string, where NAME is a macro name you choose and string is the macro value TARGET_DIR=/product/install DEBUG_LEVEL=3 COMPILE := $(CC) $(MODCFLAGS) $(AODV_FLAGS) -I$(KPATH)

Targets usually the name of a file that is generated by a program Phony targets – not the name of a file, but an action to carry out, such as `clean' to avoid a conflict with a file of the same name and to improve performance.

Explicit and Implicit Rules An explicit rule says when and how to remake one or more files, called the rule's targets An implicit rule says when and how to remake a class of files based on their names C compilation typically takes a `.c' file and makes a `.o' file foo : foo.o bar.o cc -o foo foo.o bar.o $(CFLAGS) $(LDFLAGS) Make will look for foo.c since there are no rules for foo.o

Conditionals Same basic principles as the conditionals we know and love Control what make actually "sees" in the makefile

Complex Makefile

Example Kernel AODV

References http://www.metalshell.com/view/tutorial/120/ http://vertigo.hsrl.rutgers.edu/ug/make_help.html http://www.gnu.org/software/make/manual/make.html http://www.eng.hawaii.edu/Tutor/Make/