Win with HDL Slide 4 System Level Design FPGA Roadmap Design Requirements and Flow Design Re-Use and IP Integration Coding for Performance Synthesis Requirements Verification Methodology Summary Slide 4 System Level Design States some of the key reasons why customers want system integration on a chip. It increases performance and reliability while reducing cost (usually) and power dissipation and doing all this in a smaller footprint. This is being driven by most industries in electronics but the ones that most directly impact our business are telecom, networking and the computer business (typically add-on cards for us). 4 1 2

FPGA Roadmap Density/Performance 1995 1996 1997 1998 1999 Year Virtex 1M Systems Gates 2.5Volt Power Supply 0.25/0.18 XC4000XV Largest Device XC40250XV 0.25m 2.5 Volt Power Supply 25% Faster than XL Density/Performance XC4000XL Largest Device XC4085XL 0.35m 3.3 Volt Power Supply 30% faster than EX XC4000EX Largest Device XC4036EX 0.5m 5 Volt Power Supply 30% faster than E XC4000E Largest Device XC4025E 0.5m 5 Volt Power Supply 1995 1996 1997 1998 1999 Year 3 2

Design Requirements and Flow Simulation (V)HDL Behavioral Increase Speed and Reduce Cost Design Re-Use, IPs Coding for Performance Architecture Independence Synthesis Post Synthesis Implementation Tools Post Layout 4 3

Intellectual Property Think IP at Specification IP the building block Xilinx suite includes ATM, DSP, HDLC, PCI, RISC and USB blocks IP Solution Goal Reduced cost, Increase system performance and Increase predictability Xilinx delivery vehicles IP optimized for Xilinx architecture, guaranteed functionality Parameterized cores with Core Generator, web mechanism to download new cores and links to System Level tools 5 4

Intellectual Property Delivery Vehicles AllianceCORE Program Partner Core Development and Service Program Sold and supported by partner CORE Generator Software Flexible and easy to use vehicle Cores , Application Notes & data sheets 6 5

Coding for Performance FPGAs require better coding styles and more effective design methodologies Pipelining techniques allow FPGAs to reach gate array system speeds Gate Arrays can tolerate poor coding styles and design practices 66 MHz is easy for an Gate Array Designs coded for a Gate Array tend to perform 3x slower when converted to an FPGA Not uncommon to see up to 30 layers of logic and 10-20 MHz FPGA designs 6-8 FPGA Logic Levels = 50 MHz 7 6

Effective Coding Style Case vs If-Then-Else module mux (in0, in1, in2, in3, sel, mux_out); input in0, in1, in2, in3; input [1:0] sel; output mux_out; reg mux_out; always @(in0 or in1 or in2 or in3 or sel) begin case (sel) 2'b00: mux_out = in0; 2'b01: mux_out = in1; 2'b10: mux_out = in2; default: mux_out = in3; endcase end endmodule in0 in1 in2 in3 mux_out sel module p_encoder (in0, in1, in2, in3, sel, p_encoder_out); input in0, in1, in2, in3; input [1:0] sel; output p_encoder_out; reg p_encoder_out; always @(in0 or in1 or in2 or in3 or sel) begin if (sel == 2'b00) p_encoder_out = in0; else if (sel == 2'b01) p_encoder_out = in1; else if (sel == 2'b10) p_encoder_out = in2; else p_encoder_out = in3; end endmodule in0 in1 in2 in3 sel=00 sel=01 sel=10 p_encoder_out 8 7

Effective Coding Style Reduce Logical Levels of Critical Path module critical_bad (in0, in1, in2, in3, critical, out); input in0, in1, in2, in3, critical; output out; assign out = (((in0&in1) & ~critical) | ~in2) & ~in3; endmodule in1 critical in2 out in3 module critical_good (in0, in1, in2, in3, critical, out); input in0, in1, in2, in3, critical; output out; assign out = ((in0&in1) | ~in2) & ~in3 & ~critical; endmodule in0 in1 in2 in3 out critical 9 8

Effective Coding Style Resource Sharing module poor_resource_sharing (a0, a1, b0, b1, sel, sum); input a0, a1, b0, b1, sel; output sum; reg sum; always @(a0 or a1 or b0 or b1 or sel) begin if (sel) sum = a1 + b1; else sum = a0 + b0; end endmodule a0 + b0 sum a1 + b1 sel module good_resource_sharing (a0, a1, b0, b1, sel, sum); input a0, a1, b0, b1, sel; output sum; reg sum; reg a_temp, b_temp; always @(a0 or a1 or b0 or b1 or sel) begin if (sel) begin a_temp = a1; b_temp = b1; end else begin a_temp = a0; b_temp = b0; sum = a_temp + b_temp; endmodule a0 a1 + sum sel b0 b1 10 9

Effective Coding Style Register Duplication to Reduce Fan-Out tri_en module high_fanout(in, en, clk, out); input [23:0]in; input en, clk; output [23:0] out; reg [23:0] out; reg tri_en; always @(posedge clk) tri_en = en; always @(tri_en or in) begin if (tri_en) out = in; else out = 24'bZ; end endmodule en clk [23:0]in [23:0]out 24 loads module low_fanout(in, en, clk, out); input [23:0] in; input en, clk; output [23:0] out; reg [23:0] out; reg tri_en1, tri_en2; always @(posedge clk) begin tri_en1 = en; tri_en2 = en; end always @(tri_en1 or in)begin if (tri_en1) out[23:12] = in[23:12]; else out[23:12] = 12'bZ; always @(tri_en2 or in) begin if (tri_en2) out[11:0] = in[11:0]; else out[11:0] = 12'bZ; endmodule tri_en1 en clk 12 loads [23:0]in tri_en2 [23:0]out en clk 12 loads 11 10

Effective Coding Style Design Partition - Reg at Boundary module reg_in_module(a0, a1, clk, sum); input a0, a1, clk; output sum; reg sum; reg a0_temp, a1_temp; always @(posedge clk) begin a0_temp = a0; a1_temp = a1; end always @(a0_temp or a1_temp) begin sum = a0_temp + a1_temp; endmodule a0 clk + sum a1 clk module reg_at_boundary (a0, a1, clk, sum); input a0, a1, clk; output sum; reg sum; always @(posedge clk) begin sum = a0 + a1; end endmodule a0 + a1 sum clk 12 11

Managing FPGA Speed Booster Pipeline 1 cycle a module no_pipeline (a, b, c, clk, out); input a, b, c, clk; output out; reg out; reg a_temp, b_temp, c_temp; always @(posedge clk) begin out = (a_temp * b_temp) + c_temp; a_temp = a; b_temp = b; c_temp = c; end endmodule * b + out c module pipeline (a, b, c, clk, out); input a, b, c, clk; output out; reg out; reg a_temp, b_temp, c_temp, mult_temp; always @(posedge clk) begin mult_temp = a_temp * b_temp; a_temp = a; b_temp = b; end out = mult_temp + c_temp; c_temp = c; endmodule 2 cycle a * b + out c 13 12

Synthesis Technology Requirement RTL level portability Counter Inferencing RAM Inferencing Operator Inferencing IO Insertion IO Register Mapping Architecture Dependance IP FIFO Pipeline Multiplier Dual Port RAM Design Management Hierarchy manipulation Error cross navigation Design constraints Incremental design Timing analysis 14 13

Verification Methodology Simulation (V)HDL Behavioral Why verification? Xilinx Solution Synthesis Post Synthesis Implementation Tools Post Layout 4 14

Why Verify? Average 25% reduction in design cycle Steve Winkelmans, DisplayTech. Design Design Cycle with minimal verification robust verification V Learn Implement Months Debug Verify L D 74 15

Xilinx Solution HDL & Cores Synthesis Implementation HDL Simulation (MTI, Verilog-XL, VSS) Behavioral (RTL) Post-Synthesis Post-Layout Static Timing Analysis (Xilinx) Critical path timing check Future Verification Strategy Formal Verification Rapid checking of design integrity Cycle Base Simulation More test coverage in less time through synchronous designing Static Timing Quad Motive, PrimeTime Synthesis HDL & Cores Implementation 75 16

Summary When coding, “think hardware” Synthesis support for all technologies Technology Independence via inference operators, RAM (limited), counters. Instantiation limited to RAM, FIFO and IP Exemplar RAM inference today Synplicity RAM inference in 5.0 Robust Verification Methodology Identified areas for enhancement Incremental Design, Modular Design, Improved Delay Estimation 76 17