University of Maryland Baltimore County Department of Computer Science and Electrical Engineering   CMPE 212 Laboratory (Discussion 10) Hasib Hasan ha26@umbc.edu Edward Hanson ehanson1@umbc.edu Ankit Baingane ankitb1@umbc.edu 1

Sequential Logic A type of logic circuit whose output depends not only on the present value of its input signals but also on the sequence of past inputs. Meaning, it can store a binary data. For example: TV remote. Applications: In counter , shift register, flip-flops Processor and computing units Memory units- RAM , SSD. Programmable devices (Microcontrollers, PLDs, FPGA, CPLDs)

Basic Sequential Logic Circuit S-R Latch (NOR): Characteristic table S R Qnext Action Q hold state 1 reset set X not allowed

Basic Sequential Logic Circuit S-R Latch (NAND): Characteristic table 𝑺 𝑹 Qnext Action Q not allowed 1 set reset X hold state

Fetching the Output from the Latch You need to get the output when it’s desired. You can make a provision for enabling or disabling your latch circuit. The R and S works only when E is HIGH. It’s called “Gated” latch or “Level Triggered” latch. Also “asynchronous”

Fetching the Output from the Latch Or, you can use a clock signal in place of Enable: It’s synchronous: Goes to HIGH and LOW at a fixed interval of time. It could be edge triggered: The circuit will operate only when the clock signal changes from ‘0’ to ‘1’ or, ‘1’ to ‘0’.

Latch vs. Flip-Flop The first case, the circuit without any synchronous clock signal is a latch. May or may not have enable. When it has a synchronous clock signal, it’s called a Flip-Flop In general, they’re always edge triggered.

Symbols: simple latch clocked latch

Master-Slave Flip-Flop Different configurations are possible for implementing a Flip-Flop. Master-Slave configuration is one of the commonly used ones. Consists of two identical RS latch circuits The inverter connected between the two CLK inputs ensures that the two sections will be enabled during opposite half- cycles of the clock signal. This is the key to the operation of this circuit.

JK Latch Was developed to overcome the problem in “not allowed” inputs of an S-R Latch. Now, we have made that “not allowed” input to toggle the previous output. J K Qnext Comment Q Hold 1 Reset Set 𝑸 Toggle

Master-Slave JK Flip-Flop When j =1, k = 1 and clk = 1; Q output will toggle as long as CLK is high. Thus the output will be unstable with continuously changing from HIGH to LOW. This problem is called race-around. Race-around problem can be solved by adopting the master-slave configuration called Master-Slave J-K flip-flop. Output will only change with the trigger.

Master-Slave JK Flip-Flop Characteristic table:

Characteristic table vs Excitation table Characteristic table: Tells you the next output state for a given set of inputs and present output state. Excitation table: Tells you what should be your inputs for a desired output in the next state. You’ll be needing them a lot in designing counters and other sequential logic circuits.

Master-Slave JK Flip-Flop Excitation table:

Master-Slave JK Flip-Flop IC

Master-Slave JK Flip-Flop IC IC 7476 Characteristic table:

Questions? 17