Digital Logic & Design Dr. Waseem Ikram Lecture No. 36

Recap

D flip-flop input table for X=0 Present State Next State X=0 D flip-flop inputs Q2 Q1 Q0 D2 D1 D0 1

D flip-flop input table for X=1 Present State Next State X=1 D flip-flop inputs Q2 Q1 Q0 D2 D1 D0 1

Boolean expression for D2 inputs Q2Q1/Q0X 00 01 11 10 1

Boolean expression for D1 inputs Q2Q1/Q0X 00 01 11 10 1

Boolean expression for D0 inputs Q2Q1/Q0X 00 01 11 10 1

3-bit Up/Down Counter

Input/Output Pin Definition of 3-bit Up/Down Counter CLOCK, CLEAR, X pin 1, 2, 3; Q0, Q1, Q2 pin 21, 22, 23 ISTYPE ‘reg,buffer’;

Equation Definition of 3-bit Up/Down Counter Equations Q0 := !Q0; Q1 := Q0 $ Q1 $ X; Q2 := !Q2 & !Q1 & !Q0 & X # !Q2 & Q1 & Q0 & !X # Q2 & !Q0 & !X # Q2 & Q1 & X # Q2 & !Q1 & Q0; [Q0, Q1, Q2].CLK = clock; [Q0, Q1, Q2].AR = !clear;

Test Vector Definition of 3-bit Up/Down Counter ([Clock, Clear, X] -> [Q2, Q1, Q0]) [ .c. , 0 ,.x.] -> [0 , 0 , 0 ]; [ .c. , 1 , 0 ] -> [0 , 0 , 1 ]; [ .c. , 1 , 0 ] -> [0 , 1 , 0 ]; [ .c. , 1 , 0 ] -> [0 , 1 , 1 ]; [ .c. , 1 , 0 ] -> [1 , 0 , 0 ]; [ .c. , 1 , 0 ] -> [1 , 0 , 1 ]; [ .c. , 1 , 0 ] -> [1 , 1 , 0 ]; [ .c. , 1 , 0 ] -> [1 , 1 , 1 ]; [ .c. , 1 , 0 ] -> [0 , 0 , 0 ]; [ .c. , 1 , 1 ] -> [1 , 1 , 1 ]; [ .c. , 1 , 1 ] -> [1 , 1 , 0 ]; [ .c. , 1 , 1 ] -> [1 , 0 , 1 ]; [ .c. , 1 , 1 ] -> [1 , 0 , 0 ]; [ .c. , 1 , 1 ] -> [0 , 1 , 1 ]; [ .c. , 1 , 1 ] -> [0 , 1 , 0 ]; [ .c. , 1 , 1 ] -> [0 , 0 , 1 ]; [ .c. , 1 , 1 ] -> [0 , 0 , 0 ];

Equation Definition for Truth Table based Sequential Circuit definition Equations [Q0, Q1, Q2].CLK = clock; [Q0, Q1, Q2].AR = !clear;

Truth Table definition for the 3-bit Up/Down Counter Truth_Table ([Clear, X, Q2, Q1, Q0] :> [Q2, Q1, Q0]) [ 0 ,.x., .x. , .x. , .x. ] :> [ 0 , 0 , 0 ]; [ 1 , 0 , 0 , 0 , 0 ] :> [ 0 , 0 , 1 ]; [ 1 , 0 , 0 , 0 , 1 ] :> [ 0 , 1 , 0 ]; [ 1 , 0 , 0 , 1 , 0 ] :> [ 0 , 1 , 1 ]; [ 1 , 0 , 0 , 1 , 1 ] :> [ 1 , 0 , 0 ]; [ 1 , 0 , 1 , 0 , 0 ] :> [ 1 , 0 , 1 ]; [ 1 , 0 , 1 , 0 , 1 ] :> [ 1 , 1 , 0 ]; [ 1 , 0 , 1 , 1 , 0 ] :> [ 1 , 1 , 1 ]; [ 1 , 0 , 1 , 1 , 1 ] :> [ 0 , 0 , 0 ]; [ 1 , 1 , 0 , 0 , 0 ] :> [ 1 , 1 , 1 ]; [ 1 , 1 , 1 , 1 , 1 ] :> [ 1 , 1 , 0 ]; [ 1 , 1 , 1 , 1 , 0 ] :> [ 1 , 0 , 1 ]; [ 1 , 1 , 1 , 0 , 1 ] :> [ 1 , 0 , 0 ]; [ 1 , 1 , 1 , 0 , 0 ] :> [ 0 , 1 , 1 ]; [ 1 , 1 , 0 , 1 , 1 ] :> [ 0 , 1 , 0 ]; [ 1 , 1 , 0 , 1 , 0 ] :> [ 0 , 0 , 1 ]; [ 1 , 1 , 0 , 0 , 1 ] :> [ 0 , 0 , 0 ];

State definition of the 3-bit Up/Down Counter QSTATE = [Q2, Q1, Q0]; A = [ 0 , 0 , 0 ]; B = [ 0 , 0 , 1 ]; C = [ 0 , 1 , 0 ]; D = [ 0 , 1 , 1 ]; E = [ 1 , 0 , 0 ]; F = [ 1 , 0 , 1 ]; G = [ 1 , 1 , 0 ]; H = [ 1 , 1 , 1 ];

Defining the next states using IF-THEN-ELSE State Diagram State A: if X then H else B; State B: if X then A else C; State C: if X then B else D; State D: if X then C else E; State E: if X then D else F; State F: if X then E else G; State G: if X then F else H; State H: if X then G else A;

Defining the next states using GOTO State Diagram State A: GOTO B; State B: GOTO C; State C: GOTO D; State D: GOTO E; State E: GOTO F; State F: GOTO G; State G: GOTO H; State H: GOTO A;

State Diagram of Elevator

State table for Elevator Control for REQ1, FLOOR1 and OPEN inputs Present State Next State REQ1=0 REQ1=1 FLOOR1=0 FLOOR1=1 OPEN=0 OPEN=1 W1(000) x C1(100) C1 W1 UP(110) W2(001) C2 DO C2(101) DO(111)

State table for Elevator Control for REQ2, FLOOR2 and OPEN inputs Present State Next State REQ2=0 REQ2=1 FLOOR2=0 FLOOR2=1 OPEN=0 OPEN=1 W1(000) C1 UP x C1(100) UP(110) W2(001) C2(101) C2 W2 DO(111)

Block diagram of the Elevator State Machine

Programmable Sequential Logic

Truth-Table & State Diagram

Elevator Controller

Digital Logic Design Lecture 36