A logic function f in n inputs x1, x2, ...xn and

Slides:



Advertisements
Similar presentations
Boolean Algebra and Logic Gates
Advertisements

Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 2 – Combinational Logic Circuits Part 3.
Representing Boolean Functions for Symbolic Model Checking Supratik Chakraborty IIT Bombay.
Based on text by S. Mourad "Priciples of Electronic Systems" Digital Testing: Design Representation and Fault Detection
MVI Function Review Input X is p -valued variable. Each Input can have Value in Set {0, 1, 2,..., p i-1 } literal over X corresponds to subset of values.
Class Presentation on Binary Moment Diagrams by Krishna Chillara Base Paper: “Verification of Arithmetic Circuits using Binary Moment Diagrams” by.
ECE 667 Synthesis & Verification - Boolean Functions 1 ECE 667 Spring 2013 ECE 667 Spring 2013 Synthesis and Verification of Digital Circuits Boolean Functions.
Binary Decision Diagrams. ROBDDs Slide 2 Example Directed acyclic graph non-terminal node terminal node What function is represented by the graph?
ECE Synthesis & Verification - Lecture 8 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Introduction.
Spring 07, Feb 13 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Binary Decision Diagrams Vishwani D. Agrawal James.
Boolean Functions and their Representations
Rolf Drechlser’s slides used
ECE Synthesis & Verification - L211 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Verification Equivalence checking.
Boolean Matching in Logic Synthesis. Equivalence of Functions Equivalence of two functions defined under l Negation of input variables l Permutation of.
Taylor Expansion Diagrams (TED): Verification EC667: Synthesis and Verification of Digital Systems Spring 2011 Presented by: Sudhan.
ECE Synthesis & Verification - Lecture 10 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Systems Binary.
 2001 CiesielskiBDD Tutorial1 Decision Diagrams Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA
ECE 667 Synthesis & Verification - BDD 1 ECE 667 ECE 667 Synthesis and Verification of Digital Systems Binary Decision Diagrams (BDD)
ENGG3190 Logic Synthesis “Binary Decision Diagrams” BDDs Winter 2014 S. Areibi School of Engineering University of Guelph.
IT University of Copenhagen Lecture 8: Binary Decision Diagrams 1. Classical Boolean expression representations 2. If-then-else Normal Form (INF) 3. Binary.
Logic Verification 2 Outline –Ordered Binary Decision Diagrams –Verification using OBDDs –OBDD Data Structures –OBDD Operations –Verification Example Goal.
Propositional Calculus Math Foundations of Computer Science.
Digitaalsüsteemide verifitseerimise kursus1 Formal verification: BDD BDDs applied in equivalence checking.
B. Alizadeh Advanced Logic Design (2008) 1 / 55 Decision Diagrams.
Binary Decision Diagrams (BDDs)
Boolean Algebra and Digital Circuits
Switching functions The postulates and sets of Boolean logic are presented in generic terms without the elements of K being specified In EE we need to.
November,2000University of Southern California1 Introduction to Binary Decision Diagrams - Shesha Shayee K. Raghunathan.
F = ∑m(1,4,5,6,7) F = A’B’C+ (AB’C’+AB’C) + (ABC’+ABC) Use X’ + X = 1.
CS 267: Automated Verification Lecture 6: Binary Decision Diagrams Instructor: Tevfik Bultan.
Algorithmic Software Verification V &VI. Binary decision diagrams.
Daniel Kroening and Ofer Strichman 1 Decision Procedures An Algorithmic Point of View BDDs.
Linear Algebra. Circuits The circuits in computers and other input devices have inputs, each of which is either a 0 or 1, the output is also 0s and 1s.
Chapter 2 Two- Level Combinational Logic. Chapter Overview Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR Gate Logic Laws and Theorems.
Mathematical Preliminaries
Courtesy RK Brayton (UCB) and A Kuehlmann (Cadence) 1 Logic Synthesis Multi-Level Logic Synthesis.
R. Johnsonbaugh Discrete Mathematics 5 th edition, 2001 Chapter 9 Boolean Algebras and Combinatorial Circuits.
Boolean Functions 1 ECE 667 ECE 667 Synthesis and Verification of Digital Circuits Boolean Functions Basics Maciej Ciesielski Univ.
Boolean Algebra. BOOLEAN ALGEBRA Formal logic: In formal logic, a statement (proposition) is a declarative sentence that is either true(1) or false (0).
Binary Decision Diagrams Prof. Shobha Vasudevan ECE, UIUC ECE 462.
LOGIC CIRCUITLOGIC CIRCUIT. Goal To understand how digital a computer can work, at the lowest level. To understand what is possible and the limitations.
CHAPTER 2 Boolean algebra and Logic gates
IT 60101: Lecture #121 Foundation of Computing Systems Lecture 13 Trees: Part VIII.
Chapter 12. Chapter Summary Boolean Functions Representing Boolean Functions Logic Gates Minimization of Circuits (not currently included in overheads)
Digital Logic.
CHAPTER 7 MULTI-LEVEL GATE CIRCUITS / NAND AND NOR GATES
Chapter 11 (Part 1): Boolean Algebra
Lecture 4 Nand, Nor Gates, CS147 Circuit Minimization and
Lecture 11: Hardware for Arithmetic
14:332:231 DIGITAL LOGIC DESIGN Boolean Algebra
ECE 2110: Introduction to Digital Systems
Chapter 4 Simplification of Boolean Functions Karnaugh Maps
CS 105 Digital Logic Design
ECE 3110: Introduction to Digital Systems
CHAPTER 3 SETS AND BOOLEAN ALGEBRA
ECE 331 – Digital System Design
ECE 667 Synthesis and Verification of Digital Systems
Boolean Algebra.
Boolean Algebra & Logic Circuits
CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 15 March 9 W’05 Yutao He 4532B Boelter Hall
Binary Decision Diagrams
Week 7: Gates and Circuits: PART II
Formal Methods in software development
Sungho Kang Yonsei University
Heuristic Minimization of Two Level Circuits
Binary Decision Diagrams
Logic Circuits I Lecture 3.
Analysis of Logic Circuits Example 1
A logic function f in n inputs x1, x2, ...xn and
ECE 120 Midterm 2 HKN Review Session.
Presentation transcript:

A logic function f in n inputs x1, x2, ...xn and Basic Definitions Let B = {0,1} Y = {0,1,2} A logic function f in n inputs x1, x2, ...xn and m outputs y1,y2, ...ym is a function f : Bn Ym is the input is the output For each component fi, i = 1,2, ...,m, define ON_SET:the set of input values x such that fi(x) =1 OFF_SET:the set of input values x such that fi(x) = 0 DC_SET:the set of input values x such that fi(x) = 2 Completely specified function : DC_SET = f, for fi f Incompletely specified function : DC_SET ,for some fi m=1 => a single output function m>1 => a multiple output function

Representations 1. Truth Table full adder X Y Cin Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 a multiple output function Sum : on-set = {(0 0 1), (0 1 0), (1 0 0), (1 1 1)} off-set= {(0 0 0), (0 1 1), (1 0 1), (1 1 0)} a completely specified function

Representations 1 variable 010 2. Geometrical representation 1 1 2 variables 00 01 10 11 3 variables 011 111 001 101 010 010 110 000 100 sum : on-set ={(0 0 1),(0 1 0),(1 0 0),(1 1 1)} off-set ={(0 1 1),(1 0 1),(1 1 0),(0 0 0)}

Representations 3. Algebraic representations Canonical sum of product Cout = x’yCin + xy’Cin + xyCin’ + xyCin Reduced sum of product Cout = yCin + xCin + xy = yCin + xCin + xyCin’ Multi-level representation Cout = Cin (x + y) + xy

Representations f = x1x2 + x3 x1 1 x2 x2 1 x3 x3 x3 x3 1 10 1 1 0 1 1 4. Reduced Ordered Binary Decision Diagram (ROBDD) Decision graph: f = x1x2 + x3 Terminal node: attribute value (v) = 0 value (v) = 1 Non-terminal node: index (v) = i two children low (v) high (v) Evaluate an input vector x1 1 x2 x2 1 1 x3 x3 x3 x3 10 1 1 10 1 1 0 1 1 1

ROBDD A BDD graph which has a vertex v as root corresponds to the function Fv : (1) If v is a terminal node: a) if value (v) is 1, then Fv = 1 b) if value (v) is 0, then Fv = 0 (2) If F is a nonterminal node(with index(v) = i) Fv(xi , ...xn) = xi’ Flow(v) (xi+1 , ...xn) + xi Fhigh(v) (xi+1 , ...xn)

ROBDD Reduced BDD : No distinct vertices v and v’ such that sub- graphs rooted by v and v’ are isomorphism. No vertex v with low (v) = high (v)

F=x1x2+x1x3+x1x2x3 x1 x2 x3 1 x1 x2 x3 x1 1 x2 x1 x3 1 x2 x3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x1 x2 x3 1 1 1 1 1 1 1 x1 x2 x3 1 1 1 1 x1 x2 x3 1 1 1 1 1

ROBDD Ordered BDD: if x < y, then all nodes representing x precede all nodes representing y Given an ordering of variables, reduced OBDD is canonical

ex : x1x2 + x3x4 x1 < x2 < x3 < x4 x1 1 x2 1 x3 1 x4 1 1 Example The size of OBDD depends on the ordering of variables ex : x1x2 + x3x4 x1 < x2 < x3 < x4 x1 1 x2 1 x3 1 x4 1 1

Example For a good ordering, the size of an OBDD remains reasonably small Multiplier is an exception x1 1 x3 x3 1 1 x2 x2 1 1 x4 1 1 x1 < x3 < x2 < x4

x1 x1 x1 1 1 Operations on ROBDD Apply f1 <op> f2 (f1, f2 must have the same ordering of variables, then operations can be operated on f1, f2 ) f1 f2 = (x1’g1 + x1g2)(x1’g3 + x1g4) = x1’g1g3 + x1g2g4 = x1’(g1g3) + x1(g2g4) f1 f2 f1 f2 x1 x1 x1 1 1 1 g1 g2 g3 g4 g2g4 g1g3 f1 + f2 f1 f2 etc.

ROBDD complement : f 1 f1 f2 : f1’ + f1f2 (implication) time complexity Reduced O( G log G ) Apply O( G1 G2 )

Property of ROBDD (1) Commonly encountered functions have reasonable representations.(except multiplier) (2) Complementation will not blow up the representation. (3) Canonical form so that equivalence, satisfiability checking can be done easily. (4) Multi-level representation

Representation 5. And-Inverter Graph (AIG) Simple structure And-Gates as nodes (shown as circles) with two inputs as edges (shown as arrows) Inverters edge marked with a dot

Example Ex: y = f( x1,x2,x3) =( (x1 ‧ x2 )’ ‧ (x2 ‧ x3)’)’ = ( x1 ‧ x2 ) + (x2 ‧ x3)

Start from SOP representation Convert to AIG using DeMorgans law AIG Construction Start from SOP representation Convert to AIG using DeMorgans law x1 + x2 = ( x1 + x2) ’’= ( x1 ’ ‧ x2 ’) ’ 2-input and 2-input nand 3-input and 2-input or

Size is the number of AND nodes in it AIG Attributes Size is the number of AND nodes in it Logic level is the number of AND-gates on the longest path from primary input to primary output The inverters are ignored 6 nodes, 4 levels

AIG Canonicity AIGs are not canonical ROBDDs are canonical Same function represented by two functionally equivalent AIGs with different structures Different structures can still be optimal 6 nodes, 4 levels => area optimal 7 nodes, 3 levels => speed optimal

Characteristic Function Let E be a set and A E The characteristic function A is the function XA : E -> { 0,1 } XA(x) = 1 if x A XA(x) = 0 if x A Ex: E = { 1,2,3,4 } A = { 1,2 } XA(1) = 1 XA(3) = 0 E A

Characteristic Function Given a Boolean function f : Bn -> Bm , the mapping relation denoted as is defined as The characteristic function of a function f is defined for (x,y) s.t. Xf(x,y) = 1 iff (x,y) F

Characteristic Function Ex: y = f( x1,x2 ) = x1 + x2 x1 x2 y 0 0 0 0 1 1 1 0 1 1 1 1 Fy(x1,x2,y) = x1 x2 y F 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

Operation on Logic Function Complement Intersection Union Difference XOR F is a tautology Cofactor Boolean difference Consensus operator Smoothing operator

Cofactor Cofactor operation ( restriction ) cofactor of f with respect to xi=0 cofactor of f with respect to xi=1

Cofator Cofactor with respect to any cube Ex:

Shannon Expansion

Boolean Difference is called Boolean difference of f with respect to x f is sensitive to the value of x when Ex:

Consensus Operator evaluate f to be true for x=1 and x=0 Ex:

Smoothing Operator evaluate f to be true for x=1 or x=0 Ex:

Image Computation by Smoothing Operator Computation of reachable states of a sequential finite state machine Given f : Bn -> Bm and let Use F to obtain the image of a subset A of Bn by f Compute the projection on Bm of the set F∩(A× Bm) Smoothing operator and and are used

Example for Image Computation x1 x2 y z A= {(0, 0), (0, 1)} 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 F(x1, x2, y, z) = x1 x2 y z F 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 …….

How to Build Characteristic Functions? Ex: x1 x2 y z 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 y = x1+ x2 F1 (x1, x2, y) = z = x1 F2 (x1, x2, z) = F(x1, x2, y, z) = Image computation: S{x1, x2} (F(x1, x2, y, z) )