Electrical Characteristics Practice Problems 1

Slides:



Advertisements
Similar presentations
Logic Gates.
Advertisements

Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)
3.4 Bipolar Logic 1. Diode Logic
Physical States for Bits. Black Box Representations.
ECE 331 – Digital System Design Electrical Characteristics of Logic Gates, Circuit Design Considerations, and Programmable Logic Devices.
Logic Families Introduction.
INTEGRATED CIRCUIT LOGIC FAMILY
CH111 Chapter 11 CMOS and TTL Circuits By Taweesak Reungpeerakul.
Practical Digital Design Considerations Part 1 Last Mod: January 2008 ©Paul R. Godin.
Electrical Characteristics Practice Problems 1 Last Mod January 2008  Paul R. Godin with Solutions.
Chapter 11 Logic Gate Circuitry.
3. Logic Gate 3.1 Introduction static, fully complementary CMOS psudo-nMOS, domino logic 3.2 Combinational Logic Functions combinational logic ---- specification.
Sneha.  Gates Gates  Characteristics of gates Characteristics of gates  Basic Gates Basic Gates  AND Gate AND Gate  OR gate OR gate  NOT gate NOT.
IC Logic Families Wen-Hung Liao, Ph.D.
Notes on Elmore Delay Calculations for Gate Simple Assumptions: Source/Drain/Gate Capacitance is proportional to gate width. Transistors in series share.
Logic Gates. AND gate Produces an output only if both inputs are on Input AInput BOutput (Q) Q=
Electrical Characteristics of ICs Part 3 Last Mod: January 2008  Paul R. Godin.
Electrical Characteristics of IC’s Part 2
Topic 1 Topic 1 Objectives Topic 2 Topic 2 Topic 3 Topic 3 Topic 4 Topic 4Menu.
Digital Logic Inverter Clasificacion de Circuitos y frecuencia maxima.
Electrical Characteristics of Logic Gates Gate Characteristics Last Mod: January 2008  Paul R. Godin.
Physical Properties of Logic Devices Technician Series Created Mar
Electrical Characteristics of Logic Gates
Logic Families.
Resistor Transistor Logic - RTL
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Diode Transistor Logic – DTL
Chapter 06 Logic Gate Circuitry.
EI205 Lecture 3 Dianguang Ma Fall, 2008.
ECE 3130 Digital Electronics and Design
Project Block Diagram Transmitter Receiver × 2 Input Device Protection
EI205 Lecture 5 Dianguang Ma Fall 2008.
MOS Inverters 1.
Logic Families Logic Family : A collection of different IC’s that have similar circuit characteristics The circuit design of the basic gate of each logic.
Transistor Transistor Logic – TTL (74xx and 54xx series chips)
EI205 Lecture 15 Dianguang Ma Fall 2008.
Digital CMOS Logic Circuits
Basic Digital Logic: X-OR and X-NOR Gates
KS4 Electricity – Electronic systems
KS4 Electricity – Electronic systems
NAND Gate Truth table To implement the design,
Overview Part 1 – The Design Space
Lecture 4 EGRE 254 1/26/09.
Reading: Hambley Ch. 7; Rabaey et al. Sec. 5.2
Digital Logic Families
Latches and Flip-Flops 2
Chapter #13: CMOS Digital Logic Circuits
CMOS circuits and Logic families
Lecture No. 7 Logic Gates Asalam O Aleikum students. I am Waseem Ikram. This is the seventh lecture in a series of 45 lectures on Digital Logic Design.
Counters and Registers
CSE221- Logic Design, Spring 2003 Logic Technology
Asynchronous Counters 2
ENEE 303 7th Discussion.
Basic Digital Logic: X-OR and X-NOR Gates
Chapter – 2 Logic Families.
KS4 Electricity – Electronic systems
MOS Transistors CMOS Inverter and Logic Families
Edge-Based Circuits DIGI-260 ©Paul R. Godin gmail.com.
Synchronous Counters 4: State Machine Counting
Electrical Characteristics Practice Problems #1
Latches and Flip-Flops 2
X y y = x2 - 3x Solutions of y = x2 - 3x y x –1 5 –2 –3 6 y = x2-3x.
74LS245: 3-State Octal Bus Transceiver
Chris Farrar Hex Inverter – 7404, 74LS04, and 7405
Combinational Logic Practice Problems gmail.com Jan 2015.
Lecture #18 OUTLINE Reading Continue small signal analysis
ECE 331 – Digital System Design
Chap. 8 Integrated-Circuit Logic Families
Electrical Calculations
Lecture 1: Logic Gates & Analog Behavior of Digital Systems
Presentation transcript:

Electrical Characteristics Practice Problems 1 with Solutions Last Mod January 2008  Paul R. Godin

Calculations Calculate the values for each circuit using values from the specification sheets. Use the TI specification sheets for TTL Use the OnSemi Specification sheets for CMOS Answers at the end of the presentation…

Problem #1 Determine the B to C propagation delay for the following circuit: NAND gate is a 4011B Point A is a logic Low

Problem #2 Determine the propagation delay for the following circuit, assuming the inverter is a 74S04, the NAND gate is a 4093B and the OR is a 7432.

Problem #3 Determine the fanout for a 4049UB connecting to 74LS08’s.

Problem #4 Determine the fanout for a 7400 connecting to 14584B’s.

Problem #5 Determine the noise margin for a 4011B connecting to a 7404.

Problem #6 Determine the noise margin for a 7408 connecting to 4050B’s.

Problem #7 Determine the Power requirements for a 74LS08 with: 2 gates with a high output 2 gates with a low output

Answers…

Problem #1 Solution tPLH: 250s tPHL: 250s Determine the B to C propagation delay for the following circuit: NAND gate is a 4011B Point A is a logic Low tPLH: 250s tPHL: 250s The specifications are based on the outputs. tPLH tPHL tPHL tPLH tPLH tPHL Answer is 750ηs

Problem #2 Solution Determine the propagation delay for the following circuit, assuming the inverter is a 74S04, the NAND gate is a 4093B and the OR is a 7432. tPLH: 15s tPHL: 22s tPLH: 250s tPHL: 250s tPLH: 4.5s tPHL: 5s tPLH tPHL tPHL tPLH tPLH tPHL Answer is 276.5ηs

Problem #3 Solution Determine the fanout for a 4049UB connecting to 74LS08’s. IIH: 20μA IIL: 0.4mA IOH: 1.25mA IOL: 3.2 mA Answer: Fanout = 8 Gate inputs

Problem #4 Solution Determine the fanout for a 7400 connecting to 14584B’s. IIH: 0.1μA IIL: 0.1μA IOH: 0.4mA IOL: 16mA Answer: Fanout = 4000 Gate inputs

Problem #5 Solution Determine the noise margin for a 4011B connecting to a 7404. Minimum Minimum 4011B: VOH: 4.95 V VOL: 0.05 V 7400: VIH: 2.0 V VIL: 0.8V Maximum Maximum Output Input

Problem #6 Solution Determine the noise margin for a 7408 connecting to 4050B’s. Minimum Minimum VOH: 2.4 V VOL: 0.4 V VIH: 3.5 V VIL: 1.5V Maximum Maximum Output Input Noise Margin problem!

Problem #7 Solution Determine the Power requirements for a 74LS08 with: 2 gates with a high output 2 gates with a low output ICCH: 4.8mA ICCL: 8.8mA

END January 2008 Paul R. Godin prgodin @ gmail.com