Interfacing mixed signal peripherals by protocols of packet type Emil Gueorguiev Saramov Angel Nikolaev Popov Computer Systems Department, Technical University of Sofia Kliment Ohriski blvd. No Sofia, Bulgaria phone: phone:

1. Introduction Interfacing requirements of mixed signal peripheral devices: Data flow with high transfer rate Low latencies introduced by the interface Remote analog/mixed signal units Minimized interface hardware Application groups: Test and measurement instruments – DSO, MSO, logic analyzers, protocol analyzers, data generators, AFG Digital video Industrial process control and monitoring

High-speed Universal Serial Bus (USB 2.0) key features: Signaling (maximum) data transfer rate 480 Mb/s Low complexity/cost of the interface hardware Single host multiple device architecture Packet type protocol High reliability, hardware level of data integrity checks and retries Software supported in almost all platforms and operating systems USB 2.0 host is embedded in any new computer system Backward compatibility with low- and full-speed USB1.1 devices

Cypress EZ-USB FX2 Worlds first high speed USB2.0 integrated device controller Innovative design of the peripheral side interface: Slave FIFO peripheral interface General Programmable Interface (GPIF) Smart USB 1.1/2.0 engine (Serial Interface Engine, SIE) – handles most of the USB protocol in hardware Fast enhanced 8051 compatible CPU core CPU runs firmware that can be downloaded via USB, from onboard EEPROM or directly in FLASH/PROM The CPU can exclude itself from data path (in high data rate cases) or to be involved in data processing Convenient standard peripherals: 3 timers/counters, 2 UART, I2C master controller Expanded interrupt system with vectored USB interrupts Large number of general purpose I/O lines Low power version – FX2LP

2. Reconfigurable mixed signal system The system is developed as universal laboratory equipment of Computer Systems Dept., TU-Sofia Hardware structure (data path - Fig.1) Build around FPGA Xilinx Spartan 2 that is configured from PC via JTAG port or from on board FLASH 2 channel 8-bit high-speed input analog interface, 400MS/s High speed digital interface, 8-bit 200MHz Zero Bus Turnaround (ZBT)/No Bus Latency (NOBL) SRAM USB 2.0 EZ-USB FX2 device controller Address/Data/Control Bus for expanding with high precision low speed ADC, DAC and digital I/O interfaces

Fig. 1

Software Firmware for FX2 CPU, download from PC during the FX2 initialization, or from I2C EEPROM - functionality in the current tests – initialization of USB and peripheral interface of FX2; CPU excluded from data path (AutoIn modes) PC drivers: - USB drivers of the operating system – EHCI driver, usbd.sys - general purpose FX2 device driver. In the current tests it downloads the firmware into FX2 RAM Test program - MFC based application that measures the transfer times, then calculates the data rates and write them to a file.

3. Quantum FIFO and double, triple, quad buffering The packet type of USB protocol makes possible use of quantum FIFO The dual port endpoint RAM is partitioned into blocks (256x16 in the cases of the tests). Each block is a FIFO, connected to the peripheral bus or to the SIE. The connections change when one of the buffers is full and the other – empty (Fig. 2) The transition between the states does not insert latency Double buffering is shown on Fig. 2. Triple and quad buffering use the same algorithm, but one/two FIFO blocks are added for triple/quad buffering Drawback of the quantum FIFO is the overhead when sending data that does not fill entirely the FIFO – by activation of PKTEND input or other methods

Fig. 2

4.Data transfer rate measurement methodology The data transfer rates are obtained by measuring the time, necessary to receive 10 MB for each point of the curves Time measurement is implemented by the instruction that reads the inside counter of the Pentium processor - RDTSC The received data is not processed The data verification is made outside the measured time intervals No other USB devices except the universal mixed signal system are connected to the USB

5. Peripheral interface synchronization Two data/clock domains In a system that contains peripheral device and USB controller, usually the data/clock domains are different for the controller and the peripheral device. The hardware of the peripheral interface must provide data transition from the peripheral data/clock domain to the USB data/clock domain. Peripheral interface clock source USB controller generates the interface clock The peripheral interface is synchronized with USB related clocks. If the whole peripheral device is synchronized with the interface clock, only one clock/data domain exists. This situation is difficult to implement without loss of optimality. The tests are run with interface clock from USB controller, but analog interface has a different clock. As the timing requirements of peripheral interface are relative to the USB controller clock, this option provides maximum interface data transfer rates.

The peripheral device generates the interface clock In this case the data transition from peripheral device clock domain to USB controller clock domain is implemented by level2 FIFO. Asynchronous peripheral interface In this mode the interface clock is not used externally, pseudo asynchronous mode (synchronized internally) The maximum value of data rates from the tests is near the theoretical maximum – 16.6 MB/s The write strobe SLWR_N, generated for the tests exactly meets the minimum requirements: process (CLK2X) MHz begin if CLK2X='1' and CLK2X'event then if COUNT1<24 then COUNT1 <= COUNT1 + 1; else COUNT1 <= "00000"; end if; if COUNT1<10 then SLWR_N <= '0'; -- low 50ns else SLWR_N <= '1'; -- high 70ns end if; end process;

Fig. 3

Fig. 4

Synchronous peripheral interface The read/write strobes are clock enables for FX2 FIFO Theoretical maximal value of data rate of the peripheral interface is 96MB/s at 48MHz internal clock, therefore the peripheral interface is not a bottleneck (as asynchronous interface) The test results are 35% and 74% of the USB 2.0 data transfer rate maximum (53 MB/s) The bottleneck is in the PC, it limits at 19MB/s (Windows 2000/PentiumIII-733MHz, NEC EHCI) and at 39MB/s (Windows XP SP1/Pentium4-1.5GHz, Intel EHCI) Using isochronous transfers produces similar results, but isochronous transfers are not guaranteed by USB protocol to be error free, therefore streaming is not suitable for compression methods without error correction

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Fig. 6

Analysis of the dependences Low data transfer rates when a small number of packets (1 - 5) in one DeviceIOControl indicate that calls from User Mode to Kernel Mode slows down the communication The deviation in the data transfer rates is significant an steady Small differences between data transfer rates for 2x, 3x and 4x buffering shows that 2x buffering does not lead to NAK of the IN tokens

Theoretical maximumSync, WXPAsync, WXPSync, W2KAsync, W2K Fig. 7

6. Conclusions The results for sustained data transfer rates about 75% of the maximum for bulk transfers over USB 2.0 shows that it can be used in most of the medium to high speed mixed signal systems Appropriate methods for data buffering and synchronization should be used to remove bottlenecks from data path Software data processing in high transfer rate systems should be limited or avoided The limited data transfer rates makes important high speed data compression methods