Programmable Logic Arrays, Test Review

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Presentation transcript:

Programmable Logic Arrays, Test Review Today: First Hour: Programmable Logic Arrays Section 4.1 of Katz’s Textbook In-class Activity #1 Second Hour:Test #1 Q&A, Review.

Recap: Simplifying Larger Functions Use Logic Minimization software. Example: espresso Public domain, Easy to use, yet Serious enough for the real world. .i 3 .o 3 .p 8 000 001 001 010 010 011 011 100 100 000 101 --- 110 --- 111 --- .e a2 a1 a0 b2 b1 b0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 x x x 1 1 0 x x x 1 1 1 x x x .i 3 .o 3 .p 4 0-0 001 -11 100 -01 010 -10 010 .e b2 = a1 a0 b1 = a1' a0 + a1 a0' b0 = a2' a0'

Implementing Larger Circuits: Programmable Logic Arrays Old technology: Buy chips with gates (e.g., a chip with 4 NAND gates), and wire them up to build logic circuits messy wiring, error prone takes lots of space and power Newer technology: Buy a single programmable logic array (PLA) chip Customize this chip to implement our function Can be as easy as downloading an espresso output to a “PLA programmer.”

PLA Example Need to implement the following 3-input, 4-output function: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A

Blank PLA A B C F0 F1 F2 F3

After Programming Note: F1 and F2 reuse AB 1 A B C A B B' C A C' B' C' F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A F0 F1 F2 F3

Key to Efficiency: Reuse Shared Terms F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A B' C' A A B

“Personality Matrix” Product t erm Inputs Outputs F 1 F F 1 F 1 A 1 - 1 F 1 F 2 1 F 3 1 A 1 - B 1 - C - 1 A B Reuse of terms B' C A C' B' C' A

How Programming Works Fuse on each gate input Blow the fuse with a large current - disconnect that input Use SW to do this. (Blowing the wrong fuse would be annoying.) Other technologies are also used in PLAs, besides fuses.

Everything is connected Compact Form - Before Everything is connected

Only desired connections remain Compact Form - After A B C D A B C D Only desired connections remain A B + A B C D + C D

Programmable array logic PAL Programmable array logic Minor variant on the PLA. Each output function is OR of a fixed number of terms, say 4. Does not exploit shared product terms. E.g., 16x48x8 PAL: 16 inputs (and their complements). 48 terms ANDing those inputs (or complements) (Note: 48 << 216). 8 output functions ORing those terms If these restrictions are OK, then the PAL may be cheaper.

Simple PAL

Ex: BCD to Gray Code Non- standard Gray Code sequence A 1 B C D W X Y 1 B C D W X Y Z Non- standard Gray Code sequence

K- maps K-map for W K-map for X K-map for Y K-map for Z AB AB CD 00 01 11 10 CD 00 01 11 10 00 X 1 00 1 X 01 1 X 1 01 1 X 11 1 X X 11 X X 10 1 X X 10 X X K-map for W K-map for X AB AB CD 00 01 11 10 CD 00 01 11 10 00 1 X 00 X 1 01 1 X 01 1 X 11 1 1 X X 11 1 X X 10 1 1 X X 10 1 X X K-map for Y K-map for Z

Minimized Functions W = A + B D + B C X = B C' Y = B + C Z = A' B' C' D + B C D + A D' + B' C D’ No shared terms

A B C D PAL Implementation A B D B C B C A B C D B C D A D W X Y Z

Do Activity #1 Now For Next Class: Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: Bring Randy Katz Textbook Required Reading: Sec 4.1, 4.2 of Katz This reading is necessary for getting points in the Studio Activity!