Day 15: October 13, 2010 Performance: Gates ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 15: October 13, 2010 Performance: Gates Penn ESE370 Fall2010 -- DeHon

Previously Delay as RC-charging Transistor: Capacitance, Drive Current As a function of geometry (W/L) Gate: Topology, Delay Penn ESE370 Fall2010 -- DeHon

First Order Delay t = R0C0 R0 = Resistance of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Rdrive = R0/Wn Cg = WC0 Technology independent relative delay t = R0C0 Penn ESE370 Fall2010 -- DeHon

Try again What is the delay here? Penn ESE370 Fall2010 -- DeHon

Day 14: Lesson Don’t drive large fanout with a single stage Must scale up over a number of stages …but not too many Exact number will be technology dependent Penn ESE370 Fall2010 -- DeHon

Today Miller Effect Sizing Large Fanout Data Dependent Delay Asymmetry of Inputs Impact of P & N Mobility differences Large Fanin Penn ESE370 Fall2010 -- DeHon

Gates Penn ESE370 Fall2010 -- DeHon

Data Dependent Delay Resistance depends on input values delay depends on input data t-delays assuming minsize? Penn ESE370 Fall2010 -- DeHon

How Size Equalize rise/fall times Rdrive=R0/2 Penn ESE370 Fall2010 -- DeHon

How Size For equal rise fall Rdrive=R0/2 Penn ESE370 Fall2010 -- DeHon

Input Load Input capacitance in each case? Penn ESE370 Fall2010 -- DeHon

Observe Ratio of Input Load Capacitance to Output Drive Strength: CILoad/Ids Differs with gate function Some gates give more drive per capacitive load we pay Penn ESE370 Fall2010 -- DeHon

Which Implementation is Faster? Penn ESE370 Fall2010 -- DeHon

Take Away? Penn ESE370 Fall2010 -- DeHon

Input (A)Symmetry If one input is known to be later than other, does it matter where it goes? Penn ESE370 Fall2010 -- DeHon

How Size Equalize rise/fall times Rdrive=R0/2 Penn ESE370 Fall2010 -- DeHon

Increasing Fanin What happens to input capacitance as fanin (k) increases Keeping output drive the same E.g. Rdrive=R0/2 k-input nand gate has input capacitance: Penn ESE370 Fall2010 -- DeHon

Fanin Gates slow down with fanin Less drive per input capacitance Penn ESE370 Fall2010 -- DeHon

Which is Fastest? nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 Penn ESE370 Fall2010 -- DeHon

Lesson Large gates are slow / inefficient High capacitive load / drive strength Small gates can be inefficient Need many stages Staging over moderate size gates minimizes delay Exact size will be technology dependent Penn ESE370 Fall2010 -- DeHon

Admin Project 1 Out Townley office hours this week: 2 week assignment Should have baseline done (today latest) Should be making list of ideas to make it fast Last two lectures might be relevant… Townley office hours this week: Today (Wed) 1-2pm Thursday 1-2pm Penn ESE370 Fall2010 -- DeHon

Ideas First order reason in t=R0C0 units Gates have different efficiencies Drive strength per unit input capacitance Greater N mobility (than P) favors nand over nor Large fanin and fanout slow gates Decompose into stages …but not too much Penn ESE370 Fall2010 -- DeHon