Wafer Manufacturing Farshid Karbassian

Outline Semiconductor Materials Purification Crystal pulling Grinding Czochralski Float-Zone Grinding Slicing

Outline Edge Rounding Lapping Etching Chemical Mechanical Polishing (CMP) Epitaxial Deposition

Semiconductor Materials Elemental Si, Ge Binary Compounds IV-IV SiC III-V AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InP, InAs, InSb II-VI ZnO, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS IV-VI PbS,PbSe,PbTe

Semiconductor Materials Ternary Compound AlxGa1-x As, AlxIn1-x As, GaAs1-xPx , GaxIn1-x As, GaxIn1-xP Quaternary Compound AlxGa1-x As1-ySby , GaxIn1-x As1-yPy

Wafer Lapping and Edge Grind Basic Process Steps Crystal Growth Shaping Wafer Slicing Wafer Lapping and Edge Grind Etching Polishing Cleaning Inspection Packaging Purification

3. Crystal Trimming and Diameter Grind Polysilicon Seed crystal Heater Crucible 1. Crystal Growth 2. Single Crystal Ingot 3. Crystal Trimming and Diameter Grind 4. Flat Grinding 5. Wafer Slicing 6. Edge Rounding 7. Lapping 8. Wafer Etching 9. Polishing 10. Wafer Inspection Slurry Polishing table Polishing head

Purification of Silicon Common quartz sand is mainly silicon dioxide, which can react with carbon at high temperatures. Carbon used doesn't need very high purity; it can be in the form of coal, coke or even pieces of wood. At a high temperature carbon starts to react with SiO2 to form carbon mono or dioxide.

Purification of Silicon This process generates polysilicon with about 98% to 99% purity called crude silicon or MGS. MGS has high impurities that makes it inconvenient for electronic applications. To purify MGS, the crude silicon is ground into fine powder. Then the powder is introduced into a reactor to react with HCl vapor, forming any of a number of SiHCl. MGS: Metallurgical-Grade Silicon

Purification of Silicon The chemical reaction can be expressed as: TCS (SiHCl3) vapor then goes through a series of filters, condensers and purifiers to get ultrahigh-purity liquid TCS. (9s!) TCS now has less than one impurity per billion atoms.

Purification of Silicon Purified polysilicon is obtained from TCS which is purified earlier by fractional distillation, in a large CVD reactor. The high purity polysilicon is called electronic-grade silicon, or EGS.

Purification of Silicon (cont.)

Crystal Pulling The EGS which is obtained from CVD has polycrystalline structure whereas Si which is used in fabrication of electronic devices is single crystal. The resulting polysilicon may be broken up into pieces to load into crucibles for Czochralski crystal growth or the poly rod itself could be used as the starting material for float-zone crystal growth.

Crystal Pulling (cont.) Crystallization methods: Czochralski (CZ) Float-zone (FZ)

Czochralski Crystal Growth

Czochralski Crystal Growth During CZ crystal growth, the seed and the crucible are normally rotated in opposite directions to promote mixing the liquid and more uniform growth.

Czochralski Crystal Growth

Czochralski Crystal Growth Why CZ is much more common? The CZ process is cheaper. It is capable of producing large diameter crystals, from which large diameter wafers can be cut.

Czochralski Crystal Growth 88 die 200-mm wafer 232 die 300-mm wafer Assume 1.5x1.5 cm2 microprocessor

Czochralski Crystal Growth The only significant drawback to the CZ method is that the silicon is contained in liquid form in a crucible during growth and as a result, impurities from the crucible are incorporated in the growing crystal.

Czochralski Crystal Growth Oxygen and carbon are the most significant contaminants. To avoid additional impurities from the ambient, the growth is normally performed in an argon ambient.

Float-Zone (cont.) Gas inlet (inert) Chuck Polycrystalline rod (silicon) Molten zone RF Traveling RF coil Seed crystal Chuck Inert gas out

Float-Zone

Float-Zone Not to use any crucible in the FZ method impurity levels particularly oxygen is much lowered in the resulting crystal. And it makes easier to grow high-resistivity material. Thus the FZ process is used when only high resistivity, low oxygen content or both is required.

Grinding The boule is placed in a lathelike machine to grind with a diamond wheel into a perfect cylinder. After the boule is ground to an appropriate diameter one or more “flats” are normally ground along its length.

Grinding Internal diameter wafer saw Flat grind Diameter grind Preparing crystal ingot for grinding

Grinding

Slicing The boule is sliced into individual wafers by a rapid-rotating, inward-diameter diamond-coated saw which cuts on its inside edge.

Slicing

Edge Rounding After sawing, preventing the wafer chipping during the mechanical handling, the wafer edge is ground in a mechanical process to round the sharp edges created in the slicing process.

Edge Rounding

Lapping The lapping operation is done under pressure using a mixture of alumina (Al2O3), water and glycerine to improve the flatness of the wafer to about ±2 µm, removing most of the taper and bow that results from the sawing operation. This process removes about 50 µm from both sides of the wafer

Lapping

Etching To remove any particles and damages that many still remain from sawing and lapping steps chemical etching is done as a batch process, with the wafers are loaded into cassettes and immersed in a mixture of nitric, hydrofluoric and acetic acids.

Etching (cont.)

Chemical Mechanical Polishing As the wafers are need to have one mirror finish at least, CMP is the next step. Upper polishing pad Lower polishing pad Wafer Slurry

Chemical Mechanical Polishing The slurry consists of a suspension of fine silica particles in an aqueous solution of NaOH. The rotation and pressure generate heat that drives a chemical reaction in which OH¯ from the NaOH oxidize the silicon. The SiO2 particles abrade the oxide away.

CMP

Growth of Epitaxial Silicon In some purposes to increase the purity of where devices are supposed to be fabricated, an epitaxial layer of silicon is grown on the wafer.

Growth of Epitaxial Silicon

Wafer Inspection Physical dimension Flatness Microroughness Crystal defects Resistivity Contaminations

Tracking Number 1234567890 Notch Scribed identification number

Wafers Ready for Fabrication Process

Dopant Concentration Nomenclature

Evolution of Wafer Size 2000 1992 1987 1981 1975 1965 50 mm 100 mm 125 mm 150 mm 200 mm 300 mm

Evolution of Wafer Size (cont.)

Improving Si Wafer Requirements Year (Critical Dimension) 1995 (0.35 m m) 1998 (0.25 2000 (0.18 2004 (0.13 Wafer diameter (mm) 200 300 Site flatness ( Site size (mm  mm) 0.23 (22 22) 0.17 (26 32) 0.12 26 32 0.08 36 Microroughness of front surface ( RMS) (nm) 0.2 0.15 0.1 Oxygen content (ppm) £ 24 ± 2 23 1.5 22 Bulk microdefects (defects/cm ) 5000 1000 500 100 Particles per unit area (#/cm 0.13 0.075 0.055 Epilayer thickness ( % uniformity) ( 3.0 ( 5%) 2.0 ( 3%) 1.4 ( 2%) 1.0 (

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