EE4271 VLSI Design, Fall 2016 VLSI Channel Routing

Objectives Definition of VLSI channel routing problem How to perform channel routing for width optimization Lower bound proof for channel routing Understand that channel routing problem is difficult to solve

Routing to reduce the area Routing Problem Routing to reduce the area

Routing Anatomy 3D view Top view Symbolic Layout Metal layer 3 Via Top layers have more spacing between wires Top layers higher aspect ratio (like walls) Metal layer 3 Via Metal layer 2 Metal layer 1 ©Bazargan

Vertical Routing Track Horizontal Routing Track Routing Grid Vertical Routing Track Horizontal Routing Track

Channel Routing Terminology Terminals (Gate Pins) Via Upper boundary Width (# of Horizontal Routing Tracks) Tracks Lower boundary Assume that there are only one horizontal layer and only one vertical layer, i.e., no overlap among horizontal wires and no overlap among vertical wires will be allowed.

Channel Routing Problem - I Input: Two vectors of the same length to represent the pins on two sides of the channel. One horizontal layer and one vertical layer in the routing grid. Output: Connect pins of the same net together such that there is no overlap among horizontal wires and there is no overlap among vertical wires. Minimize the channel width.

Channel Routing Problem - II 1 2 2 3 4 1 2 3 3 4 4 Example: (01220304) (12033440) where 0 = no terminal Route all the pins with the same index

A Channel Routing Example How good is it? 0 1 4 5 1 6 7 0 4 9 10 10 2 3 5 3 5 2 6 8 9 8 7 9

Is this routing with the minimum width? A Simpler Example - I Is this routing with the minimum width?

Is this routing with the minimum width? A Simpler Example - II Is this routing with the minimum width?

Lower Bound on Channel Width 1 6 1 2 3 5 6 3 5 4 2 4 1 6 1 2 3 5 1 2 3 Channel density = Maximum local density 4 5 6 6 3 5 4 2 4 Local density 1 3 4 4 4 4 2 Lower bound = 4 Lower bound on channel width = Channel density

Exercise Use minimum number of tracks to route the following nets. Is your result the best possible one?

Lower Bound Always Achievable? Is the channel routing lower bound always achievable for any channel routing problem? 1 2

A More Complex Example # columns =174, # nets=72, density =19 Routing result: number of tracks=20

# routes actually on a track max # routes allowed on a track Realistic Design Different colors refer to different wire densities. Red color means large congestion. # routes actually on a track max # routes allowed on a track Congestion= From DAC Knowledge Center

Summary Definition of VLSI channel routing problem Channel routing for width optimization Lower bound for channel routing Local Density and Channel Density Lower bound is not always achievable