NASA RTSX-SU Test Update May 10 th, 2006 Presented by Daniel Elftmann

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 2 NASA RTSX-SU Tests Overview KU1/KU2KM1/KM2KM3/KM4KU3/KU4 Part # RTSX32SU - CQ208RT54SX32S - CQ208 RTSX32SU - CQ208 Package CQ208 Foundry UMCMEC UMC Silicon Rev Original PolyResize Algo OriginalNewModified NewUMA Software SAL Quantity 300 Pattern NASA1 NASA2 Definitions: Modified New Algorithm= Targets low current antifuses; increase soak time UMA (UMC Modified Algorithm)= Targets low current antifuses; increase soak time SAL (S-Antifuse Loading)= Reduces peak currents by adding capacitance NASA2= Pattern that focuses on single and double cases of S-Antifuses and B-Antifuses

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 3 KU3/4 - Testing Conditions Operating Temperature LTOL:T A = -55ºCT J = -20ºC HTOL:T A = 125ºCT J = 146ºC Stimulus for DUTs are generated by the NASA Driver card on each burn-in board CLKA / CLKB = 8 MHz (HTOL) CLKA / CLKB = 16 MHz (LTOL) Power Supplies NASA Driver card = 5.0V V CCA = 2.5V to 3.0V (view Test Plan Summary) V CCI = 4.0V

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 4 KU3/4 - Test Plan Summary Cumulative Hours Step KU3 (150 units)KU4 (150 units) T A (ºC)V CCA (V)T A (ºC)V CCA (V) , , , , , , , , ,

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 5 KU3/4 - Test Vehicle & Device Utilization KU3/4 Test Vehicle Information Device: RTSX32SU – CQ208 Wafer Lot / Date code:D1JW21 / 0519 Per lot size: (spares) + 1 (control unit) Device Utilization Post-Combiner device utilization: SEQUENTIAL Used: 1080 Total: 1080 (100.00%) COMB Used: 1800 Total: 1800 (100.00%) LOGIC Used: 2880 Total: 2880 (100.00%) (seq+comb) IO w/ Clocks Used: 34 Total: 170 CLOCK Used: 2 Total: 2 HCLOCK Used: 0 Total: 1 IO Config (No internal pullup/down, all high slew) 2 clkbufs– TTL 12 outbufs – TTL 10 outbufs – CMOS 10 outbufs – PCI

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 6 KU3/4 - Antifuse Utilization Antifuse Type No. of Utilized Antifuses Antifuse location Total Dynamic Antifuses (11,114) F 2880Antifuse between freeway & output track G 0Antifuse between output track & 2nd, 3rd, & 4th freeway on the net H 0Antifuse between two horizontal tracks V 0Antifuse between two vertical tracks W 7Antifuse between horizontal segment & 2nd freeway on the net X 1779Antifuse between horizontal segment & freeway B 2672Antifuse between Local Track and input S 2816Antifuse between output track & input (semi-direct) I 928Antifuse between horizontal segment & input K 32Antifuse between input & horizontal NCLK0 or NCLK1, or QCLK Total Static Antifuses (24,556) J 18891Antifuse between input & horizontal NVCC or NGND M 32Antifuse for I/O configuration options Q 0Silicon Signature antifuse in silicon signature words T 0 Antifuse between output track & input that is used early in programming sequence to tie-off floating output track Y 5169Antifuse between horizontal segment & vertical NVCC or NGND Z 464Antifuse between freeway & horizontal NVCC or NGND Single S-Antifuses nets = 0 (SAL eliminated 1080 Single S-Antifuse nets) Nets with Single B-Antifuse inputs = 896 Critical K-Antifuse = 0

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 7 KU3/4 - FIT Rate Calculations High Perceptivity Medium Perceptivity Low Perceptivity (Note: Calculator can be obtained from Actel upon request)

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 8 KU3/4 - Test Vehicle Design (Combinatorial Delay Circuit) All Combinatorial (C-Cells) logic utilized in perceptive delay line circuits to achieve both high Single S-antifuse and Double S-Antifuse count Single S-Antifuses will be eliminated by SAL Designer Software enhancement!!! Common delay line input (CLKA) with 16 delay line outputs Circuit is perceptive to shifts in delay for any utilized B-Antifuse or S-Antifuse

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 9 KU3/4 - Combinatorial Delay Circuit ChipEdit Layout Type 1 SuperCluster 12 of these Type 2 SuperCluster 4 of these Cluster 1 Cluster 2Cluster 1 x 4 x 12 Delay line length 30 x 4 = 120Delay line length 30 x 3 = 90

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 10 KU3/4 - Test Vehicle Design (Sequential Delay Circuit) Sequential (R-Cells) logic utilization to achieve high S-Antifuse count Single S-Antifuse all eliminated by SAL Designer Software enhancement!!! Circuit acts like dominoes CLKB sets the line low by making CLR of Q1 active and propagates to the rest of the line CLKB sets the line high by de-activating CLR of Q1, making SET active and propagates to the rest of the line Common delay line input (CLKB) with 16 delay line outputs

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 11 KU3/4 - Sequential Delay Circuit ChipEdit Layout Type 1 SuperCluster 12 of these Type 2 SuperCluster 4 of these Cluster 1 Cluster 2Cluster 1 x 4x 12 Delay line length 30 x 2 = 60Delay line length 30 x 3 = 90

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 12 KU3/4 - ATE Coverage Static I CCI, I CCA, I PP, I KS, I SV Delay measurements for falling & rising edges 0.25 ns resolution V IH & V IL V OH & V OL Input Leakage Output Leakage

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 13 KU3/4 – Current Status KU3 Device Programming – Completed Programming yield = 158/160 (98.75%) Yield loss was due to Invalid Electronic Signature Tri-temperature Testing – Completed (All Passed) Step 1 ( 0 to 250 hours LTOL) – Completed (All Passed) Step 2 (250 to 500 hours LTOL) – In Progress (due on 05/13) KU4 Device Programming – In Progress

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 14 KU3 (250 hrs LTOL) – I CCA Measured I CCA for all KU3 Units can be seen in the graph below: Delta I CCA for all devices post 250 hrs LTOL ranges from -800 uA to 280 uA

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 15 KU3 (250hrs LTOL) – I CCI Measured I CCI for all KU3 Units can be seen in the graph below: Delta I CCI for all devices post 250 hrs LTOL ranges from -320 uA to 210 uA

May 10 th, 2006NASA RTSX-SU KU3/KU4 Test Update 16 KU3 (250 hrs LTOL) – Delta Delay Distribution Delta delay distribution for all delay lines post 250 hrs LTOL ranges from -0.5 ns to 0.5 ns