ME342E Project Update (Part II) July 27th 2006

This close to complete phase1 and 2.

1: Single Grating Construction Motivation Performance Expectation The Grating is Fixed -No Actuation-The Light encounters a single grating on its path and interacts with no other material on its path Motivation The layer of material below the grating is removed to remove Fabry-Perot physics, i.e, to remove the etalon effects Performance Expectation Removing the etalons effects eliminates the peaks at other frequencies hence leading to better filter performance

Step2, Deposited Oxide on 10 wafers Thickness:5000-7000A SiO2 PR Mask Al

Step3, Add resist on the back side Thickness:10um, SVGCOAT, Track2 SiO2 PR Mask Al

Step4, Litho (BACKSIDE), Etch SiO2 , P5000 with Endpoint detection PR Mask Al

Added 1um of PR on the front side and attached a handle wafer to it Added 1um of PR on the front side and attached a handle wafer to it. Baked for 2HR at 90C.

Tool: STSEtch Time:~3HR Step5, STS at Berkeley Si SiO2 PR Mask Al Tool: STSEtch Time:~3HR

Lesson learned: Use a thicker resist for a larger surface area. Left wafers in PRX127 for more than 50HR and Sonicator (sp?) for more than 4 hours to separate them. DIDN’T HAPPEN. Lesson learned: Use a thicker resist for a larger surface area.

Step6, Sputter Al on front side Thickness:125nm SiO2 PR Mask Al Tool: Gryphon Time: :~1HR

2: Double Grating (Perfectly Aligned) Construction The Gratings are fixed with respect to each other-No Actuation Motivation It is expected that the double grating will make the device perform as a double IR filter with better filter properties Performance Expectation Double filtering->Sharper filtering-> Faster Roll off-> Better signal quality

Step1, Double side polished Si wafer – Clean @ wbnonmetal SiO2 PR Mask Al

Step2, Deposit Oxide Thickness:5000-6000A SiO2 PR Mask Al

Step3, Deposit Poly Thickness:4-5μm SiO2 PR Mask Al

Step4, Add resist Thickness:10um SiO2 PR Mask Al Tool: SVGcoat SPR220

Step5, Litho (BACKSIDE), Etch SiO2, P5000 for 14 min. PR Mask Al

Since the etch time was too long, we got into trouble with burning resist ... Or was it resist burning. Looked identical. Lesson learned: Use a pulse method to let the wafer cool down. We tried 8 pulses and problem was solved.

New Problems: Al. chamber has been down on P5000. Hopefully it’ll be back up by Tuesday (8/1). Because of that, we couldn’t try part 1 of phase1. (Duplication of J Provine’s work). Gryphon went down today. Wafers got stuck in it while we were trying to load it. We got our masks back from Image-Tec. and guess what:

Dark field @ SNF≠ Dark field @ other places. Lesson learned: Read the order sheet carefully and even better to show them what you want.

Plans: Coat 3 SiO2 (for phase1) and 2 Poly wafers (for phase2) with negative resist and expose them with our new masks. P5000 to remove the backside Oxide and Poly on desired places. STS at Berkeley to get to the front Oxide. Sputter Al. on Gryphon. Litho. P5000 to etch the Al., Poly and SiO2 layers.

Tips/Info for other users Do not use EBR when performing STS Dektak does not measure 300 um trenches … or 200 um for that matter Ti can be etched in SF6 on the Drytek Dark field / Clear field are NOT standards – remember to check if the definition is “digitized data dark” or “digitized data clear” SPR220 does not like to be baked at 120C (and doesn’t need to be)