Overheads for Computers as Components 2nd ed.

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Presentation transcript:

Overheads for Computers as Components 2nd ed. Instruction sets Computer architecture taxonomy. Assembly language. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

von Neumann architecture Memory holds data, instructions. Central processing unit (CPU) fetches instructions from memory. Separate CPU and memory distinguishes programmable computer. CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. CPU + memory memory address CPU PC 200 data 200 ADD r5,r1,r3 ADD r5,r1,r3 IR © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Harvard architecture address CPU data memory data PC address program memory data © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. von Neumann vs. Harvard Harvard can’t use self-modifying code. Harvard allows two simultaneous memory fetches. Most DSPs use Harvard architecture for streaming data: greater memory bandwidth; more predictable bandwidth. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. RISC vs. CISC Complex instruction set computer (CISC): many addressing modes; many operations. Reduced instruction set computer (RISC): load/store; pipelinable instructions. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Instruction set characteristics Fixed vs. variable length. Addressing modes. Number of operands. Types of operands. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Programming model Programming model: registers visible to the programmer. Some registers are not visible (IR). © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Multiple implementations Successful architectures have several implementations: varying clock speeds; different bus widths; different cache sizes; etc. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Assembly language One-to-one with instructions (more or less). Basic features: One instruction per line. Labels provide names for addresses (usually in first column). Instructions often start in later columns. Columns run to end of line. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

ARM assembly language example label1 ADR r4,c LDR r0,[r4] ; a comment ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ; comment © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.

Overheads for Computers as Components 2nd ed. Pseudo-ops Some assembler directives don’t correspond directly to instructions: Define current address. Reserve storage. Constants. © 2008 Wayne Wolf Overheads for Computers as Components 2nd ed.