COMS 361 Computer Organization Title: Instructions Date: 9/16/2004 Lecture Number: 7

Announcements Homework 3 Due 9/21/04

Review Instructions MIPS arithmetic instruction format Design principles Simplicity favors regularity Smaller is faster Registers Memory organization MIPS load and store instructions and format Addressing

Outline Instructions MIPS load and store instructions and format Addressing MIPS branch instructions and format

So far Assembly language is essentially directly supported in hardware, therefore ... It is kept very simple! Limit on the type of operands Limit on the set operations that can be done to absolute minimum. If an operation can be decomposed into a simpler operation, don’t include it.

So far Syntax of Arithmetic Instructions: 1 2, 3, 4 where: 1 2, 3, 4 where: 1) operation by name 2) operand getting result (destination) 3) 1st operand for operation (source1) 4) 2nd operand for operation (source2)

So far Syntax is rigid: 1 operator, 3 operands Why? Keep Hardware simple via regularity

So far MIPS Loading words but addressing bytes Arithmetic on registers only Instruction Meaning add $s1, $s2, $s3 $s1 = $s2 + $s3 sub $s1, $s2, $s3 $s1 = $s2 – $s3 lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1

So far

Indexing Through An Array C/C++ code: A[i] = h + A[i] MIPS code assumptions Base address of A is in $s3 h is in $s2 i is in $s4 # compute the offset for index i, 4 * i add $t1, $s4, $s4 add $t1, $t1, $t1 add $t1, $t1, $s3 # compute address of the ith lw $t0, 0($t1) # load the word into $t0 add $s1, $s2, $t0 # form sum sw $s1, 0($t1) # store the word in memory

Instructions Binary Registers can map to numbers Could be thought of as numbers Pieces (fields) of instructions can be represented by numbers Concatenation of numeric pieces (fields) comprise the instruction Registers can map to numbers $s0 => 16, $s1 => 17, …, $s7 => 23 $t0 => 8, $t1 => 9, …, $t7 => 15

Arithmetic Instructions Contain three registers fields Two source operands, one destination 32 different registers 5 bits identify individual registers Called R-type instructions

R-type Instructions Instruction layout or format op: opcode, identifies the operation of the instruction rs: first source operand register rt: second source operand register rd: destination register shamt: shift amount funct: function code, identifies the specific operation op rs rt rd shamt funct

R-type Instructions Instruction layout or format bit counts add $s1, $s2, $s3 Binary form of the instruction Machine language Machine code 6 5 18 19 17 32 000000 10010 00000 100000 10011 10001

R-type Instructions Instruction layout or format 32-bits Other types of instructions need different size and numbers of fields Allow different instruction lengths Allow different instruction formats Seeking regularity causes a conflict 6 5

Immediate Instructions Frequently constants are added during program execution Increment (i++) Speed execution if these constants could be in the instruction instead of in memory MIPS provides an immediate version of some instructions, which contain a constant C/C++ code i = i + 1; MIPS code addi $s0, $s1, 1

Immediate Instructions Syntax is similar to R-type instructions Except a number needs to be stored in the instruction Where should the immediate value be put using this instruction format? Hummmmm op rs rt rd shamt funct 6 5

Data Transfer Instructions C/C++ code: b = A[8]; MIPS code: lw $t0, 32($s2) Data transfer instruction syntax 1 2, 3(4) 1) Operation (instruction) name 2) Destination register 3) Numerical offset in bytes 4) Register containing the base address of the array register contains a pointer to memory Base register

Data Transfer Instructions lw $t0, 32($s2) 16-bit address means words within a 214 range around the address in the base register can be loaded 16-bit immediate number is the same number of bits as a short integer in C/C++ op rs rt Address or immediate value 6 6 5 16

Design Principle 3 Good design demands good comprises MIPS comprise Keep all instructions the same size (32-bits) Allow different instruction formats for different types of instructions

Machine language Example: lw $t0, 32($s2) 35 18 9 32 op rs rt number

Pitfall Forgetting sequential word address in a byte addressable machine differ by the word size (in bytes), not 1 MIPS is a word aligned machine Word addresses must be a multiple of 4

Pitfall 0 1 2 3 Aligned Not Bytes in Word Word Location

Machine language Pitfall: forgetting that sequential word addresses in machines with byte addressing do not differ by 1. Many an assembly language programmer has toiled over errors made by assuming that the address of the next word can be found by incrementing the address in a register by 1 instead of by the word size in bytes. So remember that for both lw and sw, the sum of the base address and the offset must be a multiple of 4 (to be word aligned).

What does this code do? label: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 swap(int v[], int k) { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; }

Stored Program Concept Fetch & Execute Cycle Instructions are fetched (from memory) and put into a special register Bits in the register "control" the subsequent actions Fetch the “next” instruction and continue

Control Decision making instructions Alter the control flow change the "next" instruction to be executed MIPS conditional branch instructions bne $t0, $t1, Label beq $t0, $t1, Label Example C/C++ code: if(i==j) h=i+j; MIPS code: bne $s0, $s1, Label add $s3, $s0, $s1 Label: ....

Control MIPS unconditional branch instructions: j label Introduce a new type of instruction format j-type for branch instructions Example: if(i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5 else j Lab2 h=i-j; Lab1:sub $s3,$s4,$s5 Lab2: …

Control Can you build a simple for loop in MIPS assembly language?

Summary so far Instruction Meaning add $s1,$s2,$s3 $s1 = $s2 + $s3 sub $s1,$s2,$s3 $s1 = $s2 – $s3 lw $s1,100($s2) $s1=Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100]=$s1 bne $s4,$s5,L Next instr. is at L if $s4 != $s5 beq $s4,$s5,L Next instr. is at Label if $s4 == $s5 j Label Next instr. is at Label

Summary so far Instruction formats R op rs rt rd shamt funct I op rs rt 16 bit address J op 26 bit address