Introduction to Microprocessor Programming A microprocessor is a CPU on a single chip. If a microprocessor, its associated support circuitry, memory and peripheral I/O components are implemented on a single chip, it is a microcontroller. Week3

Microprocessor types Microprocessors can be characterized based on the word size 8 bit, 16 bit, 32 bit, etc. processors Instruction set structure RISC (Reduced Instruction Set Computer), CISC (Complex Instruction Set Computer) Functions General purpose, special purpose such image processing, floating point calculations And more … Week3

Microprocessor applications A microprocessor application system can be abstracted in a three-level architecture ISA is the interface between hardware and software Software Hardware C program ISA level ISA program executed by hardware FORTRAN 90 program program compiled to ISA program compiled Week3

ISA Stands for Instruction Set Architecture Provides functional specifications for software programmers to use/program hardware to perform certain tasks Provides the functional requirements for hardware designers so that their hardware design (called micro-architectures) can execute software programs. Week3

What makes an ISA ISA specifies all aspects of a computer architecture visible to a programmer Basic Instructions Instruction format Addressing modes Native data types Registers Memory models advanced Interrupt handling To be covered in the later lectures Week3

Instructions (cont.) Instructions can be written in two languages Machine language made of binary digits Used by machines Assembly language a textual representation of machine language Easier to understand than machine language Used by human beings Week3

Data types The basic capability of using different classes of values. Typical data types Numbers Integers of different lengths (8, 16, 32, 64 bits) Possibly signed or unsigned Commonly available Floating point numbers, e.g. 32 bits (single precision) or 64 bits (double precision) Available in some processors such as PowerPC BCD (binary coded decimal) numbers Available in some processors, such as 68K Non-numeric Boolean Characters Week3

Data types (cont.) Different machines support different data types in hardware e.g. Pentium II: e.g. Atmel AVR: Data Type 8 bits 16 bits 32 bits 64 bits 128 bits Signed integer  Unsigned integer BCD integer Floating point Data Type 8 bits 16 bits 32 bits 64 bits 128 bits Signed integer  Partial Unsigned integer BCD integer Floating point Week3

Registers Two types General purpose Special purpose Used for special functions e.g. Program Counter (PC) Status Register Stack pointer (SP) Input/Output Registers Stack pointer and Input/Output Registers will be discussed in detail later. Week3

General Purpose Registers A set of registers in the machine Used for storing temporary data/results For example In (68K) instruction add d3, d5, operands are stored in general registers d3 and d5, and the result are stored in d5. Can be structured differently in different machines Separated general purpose registers for data and address 68K Different numbers registers and different size of each registers 32 32-bit in MIPS 16 32-bit in ARM Week3

Program counter Special register Can be of different size For storing memory address of currently executed instruction Can be of different size E.g. 16 bit, 32 bit Can be auto-incremented By the instruction word size Gives rise the name “counter” Week3

Status register Contains a number of bits with each bit associated with CPU operations Typical status bits V: Overflow C: Carry Z: Zero N: Negative Used for controlling program execution flow Week3

Memory models Data processed by CPU is usually large and cannot be held in the registers at the same time. Both data and program code need to be stored in memory. Memory model is related to how memory is used to store data Issues Addressable unit size Address spaces Endianness Alignment Week3

Addressable unit size Memory has units, each of which has an address Most common unit size is 8 bits (1 byte) Modern processors have multiple-byte unit For example: 32-bit instruction memory in MIPs 16-bit Instruction memory in AVR Week3

Address spaces The range of addresses a processor can access. The address space can be one or more than one in a processor. For example Princeton architecture or Von Neumann architecture A single linear address space for both instructions and data memory Harvard architecture Separate address spaces for instructions and data memories Week3

Address spaces (cont.) Address space is not necessarily just for memories E.g, all general purpose registers and I/O registers can be accessed through memory addresses in AVR Address space is limited by the width of the address bus. The bus width: the number of bits the address is represented Week3

Example A hardware design that has data fetched from memory every 4 bytes Fetching an unaligned data (as shown) means to access memory twice. Week3

Instruction format Is a definition Instructions typically consist of how instructions are represented in binary code Instructions typically consist of Opcode (Operation Code) defines the operation (e.g. addition) Operands what’s being operated on Instructions typically have 0, 1, 2 or 3 operands Week3

Instruction format examples OpCode OpCode Opd OpCode Opd1 Opd2 OpCode Opd1 Opd2 Opd3 Week3

Example 1 A machine has: Instructions could be formatted like this: 16 bit instructions 16 registers (i.e. 4-bit register addresses) Instructions could be formatted like this: Maximally 16 operations can be defined. But what if we need more instructions and some instructions only operate on 0, 1 or 2 registers? OpCode Operand1 Operand2 Operand3 Week3

Addressing modes Instructions need to specify where to get operands from Some possibilities Values are in the instruction Values are in the register Register number is in the instruction Values are in memory address is in instruction address is in a register register number is in the instruction address is register value plus some offset offset is in the instruction (or in a register) These ways of specifying the operand locations are called addressing modes Week3

Immediate Addressing addw #99, d7 The operand is from the instruction itself I.e the operand is immediately available from the instruction For example, in 68K Perform d7  99 + d7; value 99 comes from the instruction d7 is a register addw #99, d7 Week3

Register Direct Addressing Data from a register and the register number is directly given by the instruction For example, in 68K Perform d7  d7 + d0; add value in d0 to value in d7 and store result to d7 d0 and d7 are registers addw d0,d7 Week3

CISC CISC stands for complex instruction set computer Each instructions can execute several low-level operations Such operations of load memory, arithmetic and store memory in one instructions Required complicated hardware support All instructions take different amount of time to execute Week3

X86 CISC architecture Words are stored in the little endian order 16 bit  32-bit  64-bit Words are stored in the little endian order Allow unaligned memory access. Current x86-processors employs a few “extra” decoding steps to (during execution) split (most) x86 instructions into smaller pieces (micro-instructions) which are then readily executed by a RISC-like micro-architecture. Application areas (dominant) Desktop, portable computer, small servers Week3

MIPS RISC processor With additional features A large family designs with different configurations Deep pipeline (>=5 stages) With additional features Clean instruction set Could be booted either big-endian or little-endian Many application areas, including embedded systems The design of the MIPS CPU family, together with SPARC, another early RISC architecture, greatly influenced later RISC designs Week3

PowerPC Superscalar RISC 32-bit, 64-bit implementation With both big-endian and little endian modes, can switch from one mode to the other at run-time. Intended for high performance PC, for high-end machines Week3