DIGITAL ON/OFF AM MODULATOR AMIT R SHARMA & AKRAM SHAZAD.

Slides:



Advertisements
Similar presentations
Spartan-3 FPGA HDL Coding Techniques
Advertisements

Table 7.1 Verilog Operators.
University of Malta ICECS 2010 Terence Zarb, Ivan Grech, Edward Gatt, Owen Casha, Joseph Micallef Presented by: Terence Zarb Department of Microelectronics.
//HDL Example 6-1 // //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.
Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.
George Mason University FPGA Design Flow ECE 448 Lecture 9.
Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.
Multiplexing Multiplexing is the set of techniques that allows the simultaneous transmission of multiple signals across a single data link. A Multiplexer.
1 Simple FPGA David, Ronald and Sudha Advisor: Dave Parent 12/05/2005.
Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
Embedded Systems Hardware:
Give qualifications of instructors: DAP
Modulation Modulation => Converts from digital to analog signal.
ECE 551 Digital System Design & Synthesis Lecture 11 Verilog Design for Synthesis.
Introduction to Counter in VHDL
Packet Features are enhanced packet management controls (Mark, Restore and Release functions) that facilitate packet retransmission or receive packet discard.
Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.
Why we need adjustable delay? The v1495 mezzanine card (A395A) have a signal transmission time about 6ns. But we need all the signals go into the look.
Estimation of IQ vector components of RF field - Theory and implementation M. Grecki, T. Jeżyński, A. Brandt.
Multiplexers and De-Multiplexers 1
Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May – 9 June 2007 Javier.
Prepared by: Careene McCallum-Rodney Multiplexor.
OV Copyright © 2011 Element K Content LLC. All rights reserved. Network Communications Methods  Data Transmission Methods  Media Access Methods.
George Mason University Finite State Machines Refresher ECE 545 Lecture 11.
Modulation and Multiplexing Broadband Transmission – A carrier is a high frequency signal that is modulated by audio, video, or data. – A radio-frequency.
Introduction to the FPGA and Labs
Chapter 2 PHYSICAL LAYER.
Class Exercise 1B.
Figure 8.1. The general form of a sequential circuit.
Digital Electronics Multiplexer
Flip Flops Lecture 10 CAP
Introduction Introduction to VHDL Entities Signals Data & Scalar Types
Instructor: Alexander Stoytchev
Each I/O pin may be configured as either input or output.
Digital Electronics Multiplexer
FPGA Implementation of Multicore AES 128/192/256
DESIGN AND IMPLEMENTATION OF DIGITAL FILTER
ECE 448 Lecture 6 Finite State Machines State Diagrams vs. Algorithmic State Machine (ASM) Charts.
Direct Digital Synthesis: Applications to Radar
Instructor: Alexander Stoytchev
Latches and Flip-flops
Instructor: Alexander Stoytchev
The Xilinx Virtex Series FPGA
Microwave Synthesisers
RTL Style در RTL مدار ترتيبي به دو بخش (تركيبي و عناصر حافظه) تقسيم مي شود. مي توان براي هر بخش يك پروسس نوشت يا براي هر دو فقط يك پروسس نوشت. مرتضي صاحب.
Hakim Weatherspoon CS 3410 Computer Science Cornell University
Modulation Modulation => Converts from digital to analog signal.
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Basic Adders and Counters Implementation of Adders
Instructor: Alexander Stoytchev
A register design with parallel load input
Overview Part 1 - Registers, Microoperations and Implementations
BASE BAND DECODER Project Team Gurrampati Venkatakrishna Reddy
Register-Transfer Level Components in Verilog
The Xilinx Virtex Series FPGA
HARDWARE IMPLEMENTATION OF TEA TINY ENCRYPTION ALGORITHM
Transmitters Advanced Course requires a detailed knowledge of Transmitters and Receivers This session covers Transmitter Block Diagrams, Oscillators and.
Sequential Logic.
BASE BAND ENCODER Project Team Shashank Tadakamadla
Switching Theory and Logic Design Chapter 5:
The Verilog Hardware Description Language
Electronics for Physicists
Christian Hackmann and Evert Nord
8085 Microprocessor Architecture
Lecture 17 Logistics Last lecture Today HW5 due on Wednesday
Presented by Mohsen Shakiba
Chapter 10 Introduction to VHDL
Instructor: Michael Greenbaum
(Sequential-Circuit Building Blocks)
Presentation transcript:

DIGITAL ON/OFF AM MODULATOR AMIT R SHARMA & AKRAM SHAZAD

DIGITAL ON/OFF AM MODULATOR AIM OF THE PROJECT To Design a dedicated hardware module that performs on/off AM MODULATION. The Modulated signal should be 8 bit sinus signal of 13.56 MHz (carrier freq). The Amplitude of the carrier signal should be configured from microcontroller. The maximum clock freq is 100 MHz.

DIGITAL ON/OFF AM MODULATOR What is on on/off AM Modulation. ? Modulation is the process of facilitating the transfer of information over a medium The process of converting information so that it can be successfully sent through a medium is called modulation In amplitude modulation the amplitude of the signal is changed in response to information and all else is kept fixed. (phase and freq)

DIGITAL ON/OFF AM MODULATOR REQUIRED WAVEORMS clk i/p o/p No i/p

DIGITAL ON/OFF AM MODULATOR OSCILLATOR MODULATOR Bit stream from base band coder of 10ns. The output is a Sine wave With a carrier freq of 13.56 MHz WISHBONE INTERFACE

DIGITAL ON/OFF AM MODULATOR Design of Oscillator The clock freq is of 100 MHz and required freq of the carrier signal should 13.56 MHz hence we can have a maximum of 8 levels for defining a sine wave. COUNTER clock WAVEOUT Reset Enable SINE LOOKUP TABLE

DIGITAL ON/OFF AM MODULATOR /2  2 Amplitude Time (ns) 

DIGITAL ON/OFF AM MODULATOR Amplitude is controlled By microcontroller using Wishbone interface Low Amplitude Reg High amplitude Reg Idle mode Reg L H oscillator H High amp MUX 1 o/p L Low amp 2 13.56 MHz Low high 3 Idle low 4 s0 s1 00-idle low 01 idle high ”0” 11 ”1” Input data stream 0/1

DIGITAL ON/OFF AM MODULATOR Loop- Repeat forOther bit i/p bit stream IF i/p bit =1 IF No input Check the I/p bit IF i/p bit=0 Sine wave generator Look up table select S0S1=’11’ OUT- A select S0S1=’10 OUT- B select S0S1=’01’ OUT-C select S0S1=’00’ OUT- D Loop- Repeat forOther bit WISHBONE High Ampl Reg Const c1 A MUX SOS1 Low Ampl Reg Const c2 B C Idle Ampl Reg Const c3 D OUT

DIGITAL ON/OFF AM MODULATOR RESULTS

DIGITAL ON/OFF AM MODULATOR Results from Matlab

DIGITAL ON/OFF AM MODULATOR RESULTS FROM VHDL SYNTHESIS REPORT HDL Synthesis Report Macro Statistics # FSMs : 1 # Multipliers : 2 8x8-bit multiplier : 2 # Adders/Subtractors : 2 7-bit adder : 1 1-bit addsub : 1 # Registers : 8 1-bit register : 6 8-bit register : 2 # Multiplexers : 3 1-bit 2-to-1 multiplexer : 1 8-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 1

DIGITAL ON/OFF AM MODULATOR Device utilization summary Selected Device: 3s4000fg900-5 Number of Slices: 11 out of 27648 0% Number of Slice Flip Flops: 6 out of 55296 0% Number of 4 input LUTs: 19 out of 55296 0% Number of bonded IOBs: 11 out of 633 1% Number of MULT18X18s: 2 out of 96 2% Number of GCLKs: 1 out of 8 12% Timing Summary Speed Grade: 5 Minimum period: 2.725ns (Maximum Frequency: 366.973MHz) Minimum input arrival time before clock: 3.470ns Maximum output required time after clock: 11.521ns Maximum combinational path delay: 7.385ns

DIGITAL ON/OFF AM MODULATOR CONCLUSION The design has been successfully implemented by us. The freq of the carrier signal comes out to be 12.73 MHz. The amplitude of the carrier signal is controllable.

DIGITAL ON/OFF AM MODULATOR THANKS FOR ATTENDING OUR PRESENTATION

DIGITAL ON/OFF AM MODULATOR Questions