AMICSA, 17-20 June 2018 Leuven, Belgium Channeltron Detector Readout ASIC in 0.35µm CMOS For Cold Solar Wind Instrument AMICSA, 17-20 June 2018 Leuven, Belgium K.W, Wong, O. D. Bernal, A. Cara, A. Fedorov, R. Baruah, R. Mathon, C. Amoros, H. Tap, B. Lavraud IRAP, Université de Toulouse, CNRS, CNES, UPS, 31000 Toulouse, France Université de Toulouse, LAAS-CNRS, INP ENSEEIHT, 31000 Toulouse, France 19/06/2018 AMICSA 2018

Outline THOR project presentation CSW Instrument description Front end ASIC Specifications Design architecture CSA design Simulation results Characterization results 19/06/2018 AMICSA 2018

THOR project M4 phase A ESA candidate in 2017 Main science objective: Exploring Plasma energization in space turbulence - How is plasma heated and particles accelerated? - How is the dissipated energy partitioned? - How does dissipation operate in different turbulence regimes? CSW Instrument (Cold Solar Wind) Thor spacecraft Thor instruments 19/06/2018 AMICSA 2018

CSW instrument detection box Channel Electron Multipliers or Channeltrons Diagram of CSW detection box Cross section view of CSW detection box 19/06/2018 AMICSA 2018

ASIC specifications Event counting performance 19/06/2018 AMICSA 2018 Parameter Value Unit Power / per channel <6.5 mW Power supply 3.3 V Input Charge [0.05 – 20] pC Linearity range (fC) 50 to 800 fC Frequency 40 MHz Input Parasitic Capacitance 10 pF Radiation with 3mm Aluminium 30 krad 19/06/2018 AMICSA 2018

Design architecture => Focus on the read out channel for the prototype ASIC (no DAC-SPI for threshold tuning) Class-A front end design: Safest design at the expense of current consumption Class-AB front end design: Safe design with current consumption optimization Class-AB front end design with Reset: Optimum current consumption 19/06/2018 AMICSA 2018

A/AB Design architecture Rf Cf Class-A/AB front end design Double pulse separation = 25ns Pulse duration = 8-13ns Current amplification: Not enough gain RC Charge amplification: Too slow CSA output in the case of RC charge amplification: => Charge amplification with a 1-ns time constant has been identified as being a good compromise but still need to be followed by an amplifier 𝑉𝑜=− 𝑄𝑖𝑛 𝐶𝑓 . 𝜏𝑓 𝜏𝑓−𝜏𝑡 . 𝑒𝑥𝑝 −𝑡/𝜏𝑓 −exp⁡(−𝑡/𝜏𝑡) 𝜏𝑓=𝑅𝑓.𝐶𝑓 𝜏𝑡~1/𝐺𝐵𝑊 19/06/2018 AMICSA 2018

CSA transistor sizing and bias point First approximation: based on GBW Mapping of transistor’s gm/Id performance for optimum power consumption Another consideration is the maximum output charge detectable at 40MHz: 20pC input charge over 8ns is equivalent to 2.5mA peak current Class A CSA needs to draw at least 2.5mA in order to remain in its linear mode of operation. 19/06/2018 AMICSA 2018

CSA Operational Amplifier choices AB class operational amplifier for Cluster AB designs: adaptive dynamic current consumption Simple A-Class one-stage operational amplifier for Cluster A designs 1st order: - Avoid any possibility of overshot - Minimum power consumption with both GBW and stability Accuracy is traded off for a clean and prompt return to the baseline 19/06/2018 AMICSA 2018

Reset AB CSA Design Architecture Makes use of AB-class amplifiers for optimum current consumption Reset reference needs to be set above 800fC input charge (50fC-800fC linear detection spec) (typically 1pC) From 50fC to 1pC, CSA is a regular RC CSA. From 1pC to 20pC, CSA is a reset CSA Much higher gain can thus be chosen at the CSA stage alleviating the need of an amplifier 19/06/2018 AMICSA 2018

Simulation example of the class AB front end 19/06/2018 AMICSA 2018

ASIC layout Front end counters ASIC: 3 versions are designed Each version is implemented as a cluster of 3 channels for crosstalk characterization Tapeout: AMS 0.35µm HVCMOS Sent on the 13th of Feb 2017 Packaging: QFN64 Die size 3 x 3.5 mm² 19/06/2018 AMICSA 2018

ASIC characterization Linear range specification: 50fC-800fC 50fC-1pC 50fC-2pC 19/06/2018 AMICSA 2018

ASIC characterization 50 2-pC events are injected @ 40MHz Parameter Spec Cluster A AB RAB Power (mW) (without LVDS) <6.5 14.5 6.25 4.2 Qmin (fC) 50 60 Qmax (pC) 20 >20 Linearity range (fC) 50 to 800 50 to 1100 60 to 1000 50 to 2000 Frequency (MHz) 40 19/06/2018 AMICSA 2018

More to come Development of an injection board > maximum counting characterization currently limited by the reverse charge created when using a signal generator followed by a capacitance Interface test ASIC-Channeltron in a Vacuum Chamber AMICSA 2018

Conclusion 3 different designs for event counting have been characterized -> 40MHz max counting have been achieved for Cluster A and AB designs -> 20MHz max counting have been achieved for the Cluster RAB design Characterization is still on going A second tape out is planned for the end of this year with DAC and SPI -> individual threshold digital tuning for each channel -> monostable pulse duration digital tuning 19/06/2018 AMICSA 2018