Data Wordlength Reduction for Low-Power Signal Processing Software Kyungtae Han May 3rd, 2004 The University of Texas at Austin May 3, 2004

Low-Power at Software Level Portable wireless computing demands minimizing power dissipation due to limited power Minimizing power consumption Reduce supply voltage Decrease switching activity Software can reduce power consumption Ordering of operation Changing of number representation Reducing of data wordlength May 3, 2004

Objectives and Problems Power analysis of digital signal processing blocks for data word length in low-power software Software level power minimization with reducing data wordlength while not changing the hardware structures Problems How much can shorter data wordlength reduce power consumption? Need formulation of power consumption according to reduced data wordlength for optimum design May 3, 2004

Power Consumption Average power consumption Switching power consumption May 3, 2004

Multiply Unit for Digital Wireless Transceivers Multiply unit is usually a major source of power consumption in typical DSP applications Many digital blocks are required multiply unit for digital wireless communications Digital filters, equalizers, FFT/IFFT, digital down/up converter, etc. Multiplier core in DSP TI 64 uses a Wallace tree with 3-2 compressors TI 62 uses a Booth multiplier May 3, 2004

Data Wordlength Reduction Fixes the size of multiplication Decreases input data wordlength Signed right shift (Least significant bit side) Move toward LSB (i.e. left shift) Arithmetic right shift (if negative) Truncation (Most significant bit side) Make LSB side to be zero values May 3, 2004

Example of Array Multiplier Transition Counts Array multiplier with data flow model 16 x16 bit array multiplier 10,000 random data Node transitions counted Without delay information Data Flow Modeling 16 x 16 bit array multiplier transition counts Input data Max Min Std Mean 16 bits 3152 383 319 1863 May 3, 2004

Wallace Multiplier Transition Counts Simulation Discrete Event Simulation: Verilog Compiler Simulator Average transition counts of all gate output All gates are assumed to have a unit gate delay Variable size Wallace multiplier Wallace Size (bits) 8 16 32 Avg. transition counts 670 4177 22021 May 3, 2004

Wallace Multiplier Transition Counts Fixed-size Wallace multiplier (32 x 32 bits) n2 rate reduction in truncation method Average transition counts for data wordlength reduction Input wordlength Truncation Signed Right Shift 32 22021 16 6138 28634 8 1383 31364 4 404 32996 May 3, 2004

Conclusion and Future Work Data wordlength reduction in MSB side decreases transition counts and power consumption In Wallace multiplier, transition counts decrease n2 rate Future work Find optimum wordlength for power and precision Comparison with Booth Radix-4 Apply for digital signal processing blocks Wordlength(n) Power (p) Error (d) [1/performance] Optimum wordlength May 3, 2004