EE 201C Homework 1 Fang Gong gongfang@ucla.edu.

Slides:



Advertisements
Similar presentations
EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.
Advertisements

UCLA Modeling and Optimization for VLSI Layout Professor Lei He
Transmission Lines Demonstration High Frequency Electronics Course EE527 Andrew Rusek Oakland University Winter 2007 Demonstration is based on the materials.
Review Lecture 2. Copyright © 2009 Pearson Education, Inc. Admin: Mid-term is in class on Wednesday. No assignment this week. Labs and discussion sessions.
Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.
04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)
Outline Noise Margins Transient Analysis Delay Estimation
Home Work #4 Due Date: 18 Mar, 2010 (Turn in your assignment at the mail box of S581 outside the ME general office) The solutions must be written on A4.
Capacitive Charging, Discharging, and Simple Waveshaping Circuits
On-Chip Inductance Extraction - Concept & Formulae – 2002
rectangular waveguides x z y 0 a b 0 TE or H mode.
Transmission Line “Definition” General transmission line: a closed system in which power is transmitted from a source to a destination Our class: only.
INTRODUCTION Interconnection wiring is gaining a significant importance in speed of modern VLSI circuits. Since the wiring may cover up to eighty percent.
EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje.
EE 201C Homework 1 Fang Gong 1.References Capacitance Calculation: n Formula based – T.Sakurai, K.Tamaru, "Simple Formulas for Two-
Fang Gong HomeWork 6 & 7 Fang Gong
11/22/2004EE 42 fall 2004 lecture 351 Lecture #35: data transfer Last lecture: –Communications synchronous / asynchronous –Buses This lecture –Transmission.
1 Interconnect/Via. 2 Delay of Devices and Interconnect.
Inductance Screening and Inductance Matrix Sparsification 1.
EE 201C Homework 1 Solution Fang Gong
Chapter 1 Interconnect Extraction Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu
1 Modeling and Optimization of VLSI Interconnect Lecture 2: Interconnect Delay Modeling Avinoam Kolodny Konstantin Moiseev.
전자파 연구실 1. Fundamentals. 전자파 연구실 1.1 Frequency and time Passive circuit elements is emphasized in high speed digital design : Wires, PCB, IC- package.
Power Distribution Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology.
HDT, 1998: Resistance, Inductance, Capacitance, Conductance per Unit Length Lossless case.
On-Chip Inductance Extraction - Concept & Formulae – 2002
EE 201C Homework 1 Zhuo Jia
Worst Case Crosstalk Noise for Nonswitching Victims in High-Speed Buses Jun Chen and Lei He.
Circuit characterization and Performance Estimation
Chapter 27. Current and Resistance
On the Efficacy of Simplified 2D On-chip Inductance Models
Electricity and magnetism Chapter Six: Current and Resistance
Topics Driving long wires..
Capacitors Calculating capacitance Energy stored in a capacitor
General Physics (PHY 2140) Lecture 6 Electrodynamics
Electromagnetic Compatibility BHUKYA RAMESH NAIK 1.
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Chapter 2 Interconnect Analysis
Chapter 2 Interconnect Analysis
Chapter 27. Current and Resistance
EE 201C Homework 2 (due Feb 3 ) Wei Wu
Chapter 1 Interconnect Extraction
DC & Transient Response
Chapter 2 Interconnect Analysis Delay Modeling
Chapter 3b Static Noise Analysis
Inductance Screening and Inductance Matrix Sparsification
Electrical Stopping Power Electrical Resistance
Circuit Characterization and Performance Estimation
Homework 2 [due Jan. 31] [1] Given the circuit as shown below and a unit step voltage source at the input node s, use SPICE to simulate the circuit and.
EE 201C Homework 2 Fang Gong
Chapter 27. Current and Resistance
Wire Indctance Consequences of on-chip inductance include:
EE201C Chapter 3 Interconnect RLC Modeling
Wei Yao Homework 4 Wei Yao
EE 201C Homework 2 (due Feb 3 ) Wei Wu
9. Inductance M is a geometrical factor! L is a geometrical factor!
Mechatronics Engineering
Microstrips as Transmission Lines
Chapter 27. Current and Resistance
EE 201C Homework 1 Zhuo Jia
EE 201C Homework 1 Fang Gong
EE 201C Homework 1 Fang Gong
Ch. 31 Self Inductance Inductance A
EE 201C Homework 1 Fang Gong
Resistance.
EE 201C Homework 1 Fang Gong
Jason Cong, David Zhigang Pan & Prasanna V. Srinivas
Aim: How do we explain resistance?
Lab: AC Circuits Integrated Science II.
Lecture 2 Electrical and Electronics Circuits. After you study, and apply ideas in this Lecture, you will: Understand differences among resistance, capacitance,
Presentation transcript:

EE 201C Homework 1 Fang Gong gongfang@ucla.edu

Email Response Time HomeWork Email Response Time for Fang Gong: Monday: 3-4pm Wednesday: 3-4pm Saturday: 9-10pm Online Office Hour (Elluminate Live! Meetings) for Fang Gong Wednesday 9-10pm Please send emails about homework during these time slots for quick response. The schedule for Wei Yao will be announced by Wei soon. HomeWork HW1: CL extraction (Fang) HW2: Elmore delay & moment calculation (Fang) HW3: MOR (Wei) HW4: crosstalk noise calculation (Wei) HW5: Yield Estimation (Fang) HW6: Temporal correlation estimation for switching currents (Fang) HW7: PDN (Wei) Fang Gong: gongfang@ucla.edu Wei Yao: weiyao@ee.ucla.edu

Homework (due Jan 22) [1] Given three wires, each modeled by at least 2 filaments, find the 3x3 matrix for (frequency-independent) inductance between the 3 wires. We assume that the ground plane has infinite size for the purpose of capacitance calculation. l l T l W W W S S H wire width: W=10um, wire thickness: T=6um, wire length: l=6000um, wire spacing: S = 5um, distance to ground: H=5um, Copper electrical resistivity 0.0175e-6 Ωm2/m (room temperature), µ =1.256×10−6H/m, free space 0=8.85×10 -12F/m

Discretization and L calculation Discretize 3 wires into 6 filaments. Step 1.1 Filament 6 Filament 1 T l S W Discretization and L calculation Discretize 3 wires into 6 filaments. For each filament, calculate its self-inductance with (e.g.) For each pair of filament, calculate the mutual inductance with (e.g.) Different filaments and formulae may be used for better accuracy.

Step 1.2 Calculate inductance matrix of three wires Mutual Inductance Self Inductance If k=m, Lpkm is the self Lp for one conductor T l S W Lpkm is the mutual inductance between conductor Tk and Tm Lpij is the mutual inductance between filament i of Tk and filament j of Tm Lpij can be negative to denote the inverse current direction. L matrix from FastHenry =[ 8.0133e-09 6.8039e-09 6.1751 e-09 6.8039e-09 8.0133e-09 6.8039e-09 6.1751e-09 6.8039e-09 8.0133e-09]

Capacitance Calculation Step 1.3 Capacitance Calculation Cap. from FastCap: C3=312.86e-15 F C1=C5=251.54e-15 F C2=C4=112.98e-15 F

Step 1.4 Resistance Calculation Copper electrical resistivity 0.0175e-6 Ωm2/m (room temperature), l is length of wire A is area of wire’s cross section time

[2] Build the RC and RCL circuit models in SPICE netlist for the above wires. (suggest to use matlab script to generate matrix and thus SPICE netlist)

[3] Assume a step function applied at end-end, compare the waveforms at the far-end for the central wire using SPICE transient analysis for (a) RC and RLC models and (b) rising times (e.g., 20ns). Suggested Input: VDD 1 0 PULSE(0 1 0 20ns) Output volt 1 20ns 50ns time Input

RC model RLC model