Heterogeneous and Reconfigurable Computing Lab

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Presentation transcript:

Heterogeneous and Reconfigurable Computing Lab Lab Director: Jason D. Bakos

Heterogeneous and Reconfigurable Computing Group Objective: develop technologies to improve computer performance Processor Generation Max. Clock Speed (GHz) Max. Numberof Cores Max. RAM Bandwidth (GB/s) Max. Peak Floating Point (Gflop/s) Max. L3 cache (MB) Core (2006) 3.33 4 25.6 107 8 Penryn (2007) Westmere (2010) 3.60 6 173 12 Ivy Bridge (2013) 3.70 355 15 Broadwell (2015) 3.80 365 30

Moore’s Law? Processor Generation Transistor size (nm) Number of transistors (millions) Core (2006) 65 105 Penryn (2007) 45 228 Westmere (2010) 32 382 Ivy Bridge (2013) 22 624 Broadwell (2015) 14 1300 Cannonlake (2017) 10 2600 ?? (2020) 7 5200 ?? (2022) 5 10400 ?? (2025) 3 20800 ?? (2027) 1 41600 Si atom spacing = 0.5 nm

New Capabilities What about iPhone 6s 4K video? What about XBox One graphics?

All Modern CPUs are Heterogeneous

All Modern CPUs are Heterogeneous Apple A5x Apple A6 Apple A7 Apple A8 Apple A9 Apple A10

Heterogeneous and Reconfigurable Computing Lab We’re in good shape for graphics and video What about scientists, engineers, and computational finance? For these, we need emerging processing technologies Digital Signal Processors: Manycore Processors: Our work: Applications Development tools

Field Programmable Gate Arrays (FPGAs)

Heterogeneous Computing with FPGAs Convey HC-1

Emerging Technologies: Processor-in-Memory Micron Automata Processor: IBM Neuromorphic Processor

Contact Information Lab: Swearingen 3D15 Office: Swearingen 3A45 jbakos@sc.edu Graduate Students: Madushan Abeysinghe Lacie Cochran Rasha Karakchi Ivan Panchenko Konstantin Rubin Undergraduate Students: Charles Daniels Joshua Livingston Viraj Patel Scottie Scott Manal "Mae" Khawaja