Lecture 17 PicoBlaze I/O & Interrupt Interface ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 16, PicoBlaze I/O Interface Chapter 17, PicoBlaze Interrupt Interface ECE 448 – FPGA and ASIC Design with VHDL

Syntax and Terminology Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) s7 ab PORT(2) PORT((sa)) RAM(4) Value at register 7 Value ab (in hex) Input value from port 2 Input value from port specified by register a Value from RAM location 4

Addressing modes Immediate mode ADDCY s2, 08 s2 + 08 + C  s2 SUB s7, 7 Direct mode INPUT s5, 2a ADD sa, sf PORT(2a)  s5 sa + sf  sa Indirect mode INPUT s9, (s2) STORE s3, (sa) PORT((s2))  s9 s3  RAM((sa))

Output Decoding of Four Output Registers ECE 448 – FPGA and ASIC Design with VHDL

- - Output Instructions C Z OUTPUT OUTPUT sX, KK PORT(KK) <= sX DIR OUTPUT sX, (sY) PORT((sY)) <= sX DIR IND

Timing Diagram of an Output Instruction ECE 448 – FPGA and ASIC Design with VHDL

Truth Table of a Decoding Circuit ECE 448 – FPGA and ASIC Design with VHDL

- - Input Instructions C Z INPUT INPUT sX, KK sX <= PORT(KK) DIR INPUT sX, (sY) sX <= PORT((sY)) DIR IND

Block Diagram of Four Continuous-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

Timing Diagram of an Input Instruction ECE 448 – FPGA and ASIC Design with VHDL

Block Diagram of Four Single-Access Ports ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL FIFO Interface clk rst clk rst FIFO din dout 8 8 full empty write read ECE 448 – FPGA and ASIC Design with VHDL

Operation of the First-Word Fall-Through FIFO ECE 448 – FPGA and ASIC Design with VHDL

Operation of the “Standard” FIFO B C D −−−−− ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL Interrupt Flow ECE 448 – FPGA and ASIC Design with VHDL

Timing Diagram of an Interrupt Event ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL

Interrupt Related Instructions RETURNI ENABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 1; C<= PRESERVED C; Z<= PRESERVED Z RETURNI DISABLE I <= 0; C<= PRESERVED C; Z<= PRESERVED Z ENABLE INTERRUPT I <=1; DISABLE INTERRUPT I <=0;

Interrupt Interface with a Single Event ECE 448 – FPGA and ASIC Design with VHDL

Interrupt Interface with Two Requests ECE 448 – FPGA and ASIC Design with VHDL

Time-Multiplexed Seven Segment Display ECE 448 – FPGA and ASIC Design with VHDL

Block Diagram of the Hexadecimal Time-Multiplexing Circuit ECE 448 – FPGA and ASIC Design with VHDL

ECE 448 – FPGA and ASIC Design with VHDL Hexadecimal Multiplexing Circuit Based on PicoBlaze and mod-500 Counter ECE 448 – FPGA and ASIC Design with VHDL