8253 – PROGRAMMABLE INTERVAL TIMER (PIT)

What is a Timer? Timer is a specialized type of device that is used to measure timing intervals. Timers can be categorized to two main types. A timer which counts upwards from zero for measuring elapsed time is often called a stopwatch; a device which counts down from a specified time interval is more usually called a timer. Timers may be designed in software or in hardware. When the microprocessor needs to generate a time delay, the processor can elapse time simply using a delay routine.

Need for a dedicated Timer IC like 8253 When a specialized IC is used for the generation of delays and waveforms of different frequencies, microprocessor becomes free from these tasks and this minimizes the software overhead of the processor. Computer systems usually have at least one hardware timer. These are typically digital counters that either increment or decrement at a fixed frequency, which is often configurable, and which interrupt the processor on reaching zero is one such hardware timer.

What is 8253 Timer? Intel 8253 programmable Timer/ counter is a specially designed chip for Intel microcomputer applications which require timing and counting operations. Designed for being compatible with INTEL microprocessors like 8085,8086, 80X is an advanced version of /8254 are programmable using three 16-bit counters. Each counter has 2 input pins, Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a 16-bit count is loaded in its register. On command, it begins to decrement the count until it reaches 0, then it generates a pulse that can be used to interrupt the CPU.

8253 / 8254 Contains 3 16-bit software programmable counter 8 bit data bus interface CS i/p to assert address decoder 2 address i/p A0 & A1 2.6 / 8 MHz clock i/p(CLK) GATE i/p  external signal to start / stop counter GATE = 1  Counter enable counting GATE = 0  Counter disable OUT pin  O/P signals 5

Features of 8253 / 54 It has three independent 16-bit down counters. It can handle inputs clocks from DC to 10 MHz. These three counters can be programmed for either binary or BCD count. It is compatible with almost all microprocessors has a powerful command called READ BACK command, which allows the user to check the count value, the programmed mode, the current mode, and the current status of the counter I/p clock frequency 2.6Mhz I/p clock frequency 8 Mhz Doesn’t have Read back feature Have read back feature

8253 The timers are basically 16 - bit down counters that counts at HIGH to LOW transition of the CLK input. Each timer may be programmed to operator in one of the six modes, independent of the mode of operation of the other two timers. The timers are software programmable. The maximum clock input to the timer is 2.6 MHz. Each counter can be programmed separately to divide the input frequency by a number from 1 to (2 16 )

Functional Block diagram of 8253

Pin Diagram and Address Decoding

Data Bus Buffer

Control Register

Counters Each of the timers has three pins associated with it. Clock (CLK) input, gate (GATE) control input and output (OUT). CLK - This clock input causes the timer to decrement. The maximum clock frequency is 2.6MHz. Counters operate at HIGH to LOW transition (the negative edge) of this clock input. GATE - The gate input pin is used to initiate or enable counting. The exact effect of the gate signal depends on which of the six modes of operation is chosen. OUTPUT- The output pin provides an output from the timer. Its actual use depends on the mode of operation of the timer. The counter can be read “on the fly” without inhibiting gate pulse or clock input.

Operations for Various Control Inputs

Internal Block diagram of a counter CR M & CR L - Counter Register MSB and LSB CE – Counting Element OL M & OL L - Output Latch (MSB & LSB)

Control Word Format

System Interface

Write Operations Only two conventions need to be remembered: 1) For each Counter, the Control Word must be written before the initial count is written. 2) The initial count must follow the count format specified in the Control Word (LSB only, MSB only, or LSB and then MSB).

Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress. This is easily done in the There are three possible methods for reading the counters: a simple read operation, the Counter Latch Command, and the Read-Back Command. For simple read the selected counter must be inhibited by using either the GATE input or external logic. Otherwise, the count may be in the process of changing when it is read, gives an undefined result.

Counter Latch Command The selected Counter's output latch (OL) latches the count at the time the Counter Latch Command is received. This count is held in the latch until it is read by the CPU. This allows reading the contents of the Counters ``on the fly'' without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one Counter. Each latched Counter's OL holds its count until it is read.

COUNTER New counts are loaded and Counters are decremented on the falling edge of CLK. The largest possible initial count is 0; this is equivalent to 2^16for binary counting and 10^4 for BCD counting. The Counter does not stop when it reaches zero. In Modes 0, 1, 4, and 5 the Counter ``wraps around'' to the highest count, either FFFF hex for binary counting or 9999 for BCD counting, and continues counting. Modes 2 and 3 are periodic; the Counter reloads itself with the initial count and continues counting from there.

Modes of Mode 0: Interrupt on Terminal Count Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially low, and will remain low until the Counter reaches zero. OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter.

Mode 1 :Programmable one Shot OUT will be initially high. OUT will go low on the CLK pulse following a trigger and will remain low until the Counter reaches zero. OUT will then go high and remain high until the next count is loaded or a trigger is applied.

MODE 2: Rate Generator This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time Clock interrupt. OUT will initially be high. When the initial count has decremented to 1, OUT goes low for one CLK pulse. OUT then goes high again, the Counter reloads the initial count and the process is repeated. Mode 2 is periodic; the same sequence is repeated indefinitely. For an initial count of N, the sequence repeats every N CLK cycles.

MODE 3: Square Wave Generator Mode 3 is similar to Mode 2 except for the duty cycle of OUT signal. OUT will initially be high. When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3 is periodic; the sequence above is repeated indefinitely. An initial count of N results in a square wave with a period of N CLK cycles.

MODE 4: Software Triggered Strobe OUT will be initially high. When the initial count expires, OUT will go low for one CLK pulse and then go high again. GATE = 1 enables counting The counting sequence is ``triggered'‘ by writing the initial count.

If a new count is written during counting, it will be loaded on the next CLK pulse and counting will continue from the new count. If a two-byte count is written, the following happens: 1) Writing the first byte has no effect on counting. 2) Writing the second byte allows the new count to be loaded on the next CLK pulse. This allows the sequence to be ``retriggered'' by software. OUT strobes low N a 1 CLK pulses after the new count of N is written.

MODE 5: Hardware Triggered Strobe OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial count has expired, OUT will go low for one CLK pulse and then go high again. After writing the Control Word and initial count, the counter will not be loaded until the CLK pulse after a trigger.

If a new count is written during counting, the current counting sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there.

Example 1 Engr 4862 Microprocessors

Example 2 Engr 4862 Microprocessors

Example 3 What instructions are needed to program Counter 0 for BCD counting in mode 4? Initial count is 4788H. Solution : Control Word = = 39H Counter 0 LSB & MSB Mode 4 BCD MOV AL,39H OUT CWR,AL MOV AL,88 OUT Counter0,AL ; Counter0 =8-bit address of counter0 MOV AL,47 OUT Counter0,AL

Example 4 What instructions are needed to program Counter 2 for binary counting in mode1, with an initial count of A0H? Solution Control Word = (92H) Program MOV AL, 92H OUT CWR,AL ; CWR= Address of Control Register MOV AL,0A0H OUT Counter2,AL ; Counter2 = 8-bit address of counter2