C Model Sim (Fixed-Point) -A New Approach to Pipeline FFT Processor Presenter: Chia-Hsin Chen, Yen-Chi Lee Mentor: Chenjo Instructor: Andy Wu

Outline FFT Review FFT on Hardware What’s Fixed-Point Model Analysis RTL Implementation Conclusion & Future Works Reference 2019/4/7 Owen, Lee

FFT Review An efficient algorithm computes DFT Twiddle Factor: 2019/4/7 Owen, Lee

Radix-22 DIF Algorithm Proposed by S. He and M. Torkelson Applying a 3-dimensional linear index map 2019/4/7 Owen, Lee

Radix-22 DIF Algorithm (cont.) 2019/4/7 Owen, Lee

R22SDF Pipeline FFT Example: N=256 2019/4/7 Owen, Lee

Floating Point vs Fixed-point Use many bits to represent a number More precise but more computationally demanding Fixed-point Use finite bits to represent a number For hardware implementation 2019/4/7 Owen, Lee

Fixed-Point Model Quantization Saturation Truncation input & twiddle factor Saturation BF2I & BF2II Truncation multiplication 2019/4/7 Owen, Lee

Fixed-Point Model (Cont.) Quantization For initial values (input & twiddle factor) Table look up techniques Saturation For addition If there is a carry-out from MSB, set the number to maximum Truncation For multiplication Store the required bits form MSB, and omit the rest 2019/4/7 Owen, Lee

C/C++ Simulation 2019/4/7 Owen, Lee

Signal-of-Quantization-Noise Ratio SQNR : ratio of signal power to noise power Error range lies in ±1/2 LSB For each additional bit, the SQNR goes up by about 6dB 2019/4/7 Owen, Lee

Requirements 64-point R22SDF Dynamic range for input data:[-4,4] Number of bits for input data:10~14 Number of bits for output data:16~20 SQNR≧50dB Evaluation Equation: Score = Area * (clock period)2 2019/4/7 Owen, Lee

Analysis Overview Worst case for integer part : input x[n]=4 for n=0~63 → maximum output X[0]=4*64=256 → needs 8 bits for integer part But it is not often the case Based on the simulation result, 7 bits is enough 2019/4/7 Owen, Lee

Analysis Overview(Cont.) Fractional part and twiddle factor are closely related Fix one of them and alter the other, the effect is not obvious Therefore, fractional part and twiddle factor have to be increased simultaneously 2019/4/7 Owen, Lee

Plotting (Fix Integer Part) Fix integer part(5 – 8 bits) 2019/4/7 Owen, Lee

Average Case vs Single Case 2019/4/7 Owen, Lee

Plotting (Fix Fractional Part) Fix fractional part(7 – 10bits) 2019/4/7 Owen, Lee

Plotting (Fix Twiddle Factor) Fix twiddle factor(8 – 11bits) 2019/4/7 Owen, Lee

Average SQNR Table (7-bit integer part) frac\twi 6 7 8 9 10 11 12 13 5 33.5778 35.2070 37.5579 38.8910 39.3686 39.5589 39.6900 39.6237 35.6725 37.8124 41.4096 43.8977 44.9417 45.3195 45.4752 45.5751 36.7447 39.3552 43.9892 48.0684 50.0453 50.8486 51.2961 51.4483 37.2861 40.1783 45.5570 50.8939 54.2680 55.9788 56.8690 57.1086 37.6925 40.5367 46.2683 52.6784 57.2449 60.0804 62.0658 62.5697 37.7501 40.6730 46.7541 53.5746 59.0382 63.1174 66.3099 67.2398 37.8557 40.8907 46.9100 53.8641 59.9621 64.9456 69.5297 71.0005 37.8833 40.8881 47.0758 54.1090 60.3129 65.9172 71.5897 73.5548 2019/4/7 Owen, Lee

Possible Sets 2019/4/7 Owen, Lee

RTL Realization Just for functional work Word-lengths are the same through the whole process Integer : 8 bits (including sign bit) Fractional : 8 bits Twiddle : 12 bits (including sign bit) Omit area and timing consideration 2019/4/7 Owen, Lee

RTL Realization (Cont.) 16 points 64 points Logic elements: 2990 Registers : 2054 fmax : 21.46MHz 2019/4/7 Owen, Lee

RTL Realization (Cont.) Memory storage reducing Symmetry of twiddle factor Area reducing Different word-lengths of adder and multiplier Power saving Treat delay block as RAM 2019/4/7 Owen, Lee

Conclusion & Future Works We find some possible sets that meet the requirement Apply these sets of wordlengths to our RTL model Take area & clock period into consideration Power, if possible 2019/4/7 Owen, Lee

References S. He and M. Torkelson. “A new approach to pipeline FFT processor.” IEEE Proceedings of IPPS ’96. S. He and M. Torkelson. “Designing Pipeline FFT Processor for OFDM (de)Modulation.” ISSSE, pp. 257-262, Sept. 1998. J. Y. Oh and M. S. Lim. “New Radix-2 to the 4th Power Pipeline FFT Processor.” IEICE Trans. Electron., Vol.E88-C, No.8 Aug. 2005 E. E. Swartzlander, W. K. W. Young, and S. J. Joseph. “A radix 4 delay commutator for fast Fourier transform processor implementation.” IEEE J. Solid-State Circuits, SC-19(5):702-709, Oct. 1984. C. D. Thompson. “Fourier transform in VLSI.” IEEE Trans. Comput., C-32(11):1047-1057, Nov.1983. Y. Jung, Y. Tak, J. Kim, J. Park, D. Kim, and H. Park. “Efficient FFT Algorithm for OFDM Modulation.” Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology. Vol.2 pp.676-678, 2001. A. M. Despain. “Very Fast Fourier Transform Algorithms Hardware for Implementation.” IEEE Trans. on Computers, Vol. c-28, No. 5, May 1979 A. –Y. Wu. “CORDIC.” Slides of Advanced VLSI Y. H. Hu. “CORDIC-based VLSI architectures for digital signal processing.” IEEE Signal Processing Magazine. Pp. 16-35. July 1992 J. G. Proakis. D. G. Manolakis. “Digital signal processing” 3rd edition, Prentice Hall 2019/4/7 Owen, Lee

Thanks for Your Attention Q & A ? 2019/4/7 Owen, Lee