1-2 – Central Processing Unit

Central Processing Unit

Introduction (c) 2018

System architecture (c) 2018 How all the different hardware components connect together Central Processing Unit (CPU) consists of the following: Arithmetic Logic Unit (ALU) Control Unit (CU) Clock Bus Watch http://tiny.cc/systemarchitecture from BBC Bitesize for an overview of the system architecture (c) 2018

Von Neumann Architecture

Textbook reading Read pages 6-7 of Chapter 1 – Computer Systems from The Ultimate GCSE Computer Science Textbook (c) 2018

Von Neuman Architecture 1 John von Neumann Mathematician in the 1940s Identified that data and programs could be stored in the same memory Only one set of RAM required for both data and programs Other architectures also used in many smartphones eg Harvard architecture (c) 2018

Von Neumann Architecture 2 John von Neumann described system architecture as comprising: CPU Control Unit Input Output Arithmetic Logic Unit Memory (c) 2018

Arithmetic Logic Unit - ALU Part of CPU Carries out arithmetic calculations Addition Subtraction Shifts (multiplication and division) Carries out logical operations AND OR NOT Less Than < Greater Than > 5 + 6 = 11 if x > y (c) 2018

Control Unit - CU (c) 2018 Part of CPU Manages the execution of instructions Ensures all components perform tasks at the correct time Responsible for the fetch-execute cycle Analogy: a conductor for an orchestra (c) 2018

Clock (c) 2018 A signal to synchronise tasks Clock cycle is known as a tick Each cycle has high state Low state high one cycle (tick) Tick low Tick (c) 2018

Bus (c) 2018 System bus connects: Three buses: CPU Memory Input/Output control bus (control signals) address bus (memory addresses) data bus (instructions and data items) (c) 2018

Fetch-Execute cycle (c) 2018

Textbook reading Read page 8 of Chapter 1 – Computer Systems from The Ultimate GCSE Computer Science Textbook (c) 2018

Fetch-execute cycle (c) 2018 During one cycle: Fetch next instruction from memory Decode instruction Execute the instruction 01011101 STORE 13 (c) 2018

http://tiny.cc/fetchexecute (3:12 to 4:42) - Fetch-Execute Cycle

Registers used in Fetch-execute cycle Program counter - PC address of next instruction in memory (also known as instruction address register – IAR) Memory address register – MAR address of instruction during fetch phase OR address to retrieve data from during execute phase Memory data register – MDR current data that has been fetched from memory OR is about to be stored in memory (also known as the memory buffer register – MBR) Current instruction register – CIR instruction to be executed Accumulator – ACC result of the current calculation Registers areas of memory in the CPU hold data and memory addresses CPU   M A R P C C U M D R C I R It’s advisable to only cover the following slides with grade 6+ students and don’t be concerned if grade 6 students have difficulty understanding it. It’s only ever going to be a small number of marks on an exam paper that are targeted at the highest grade(s). A L U A C C (c) 2018

http://tiny.cc/fetchexecutefull - detailed explanation of Fetch-Execute Cycle

Fetch stage - 1 CPU RAM (c) 2018 Address Bus C U Data Bus A L U The address in memory of the next instruction is already stored in the Program Counter (PC) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1    2  3  4 25  5  6 M A R - P C - Data Bus C U M D R - C I R - A L U Control Bus A C C - (c) 2018

Fetch stage - 2 CPU RAM (c) 2018 The address in the Program Counter (PC) is copied to the Memory Address Register (MAR) The Control Unit sends the contents of the Memory Address Register to RAM RAM   CPU   Address Bus Address Contents  0 LOAD 4  1    2  3  4 25  5  6 M A R - P C - Data Bus C U M D R - C I R - A L U Control Bus A C C - (c) 2018

Fetch stage - 3 CPU RAM (c) 2018 Address Bus C U Data Bus A L U The instruction is now retrieved from memory and sent along the data bus to the Memory Data Register (MDR) The instruction is then copied from the Memory Data Register (MDR) to the Current Instruction Register (CIR) Finally the value of the Program Counter is increased by one ready for the next instruction after the fetch execute cycle RAM   CPU   Address Bus Address Contents  0 LOAD 4  1    2  3  4 25  5  6 M A R - P C - LOAD 4 Data Bus 1 C U M D R - C I R - LOAD 4 A L U Control Bus A C C - (c) 2018

Decode stage CPU RAM (c) 2018 The instruction in the Memory Data Register (MDR) is decoded by the Control Unit (CU) LOAD is recognised as the op-code (instruction) and 4 as the operand (memory location) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1    2  3  4 25  5  6 M A R - P C - Data Bus 1 C U M D R - C I R - LOAD 4 LOAD 4 LOAD 4 A L U Control Bus A C C - (c) 2018

Execute stage - 1 CPU RAM (c) 2018 The memory address is copied from the CIR to the Memory Address Register (MAR) It is then passed along the address bus to main memory (RAM) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1    2  3  4 25  5  6 M A R - P C - Data Bus 4 1 C U M D R - C I R - LOAD 4 LOAD 4 LOAD 4 4 A L U Control Bus A C C - (c) 2018

Execute stage - 2 CPU RAM (c) 2018 The data at that memory address is passed to the Memory Data Register (MDR) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1    2  3  4  25  5  6 M A R - P C - Data Bus 4 1 C U M D R - C I R - LOAD 4 LOAD 4 A L U Control Bus A C C - 4 25 (c) 2018

Execute stage - 3 CPU RAM (c) 2018 Address Bus C U Data Bus A L U The instruction from the Current Instruction Register is then executed on the data in the MDR In this example, 25 is loaded from the Memory Data Register (MDR) to the Accumulator (ACC) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1    2  3  4 25  5  6 M A R - P C - Data Bus 4 1 C U M D R - C I R - 25 25 LOAD 4 LOAD A L U Control Bus A C C - (c) 2018

Cycle completed The first fetch-execute cycle is now completed With a 2 GHz processor, that took just half a billionth of a second (c) 2018

Textbook reading Read pages 9-10 of Chapter 1 – Computer Systems from The Ultimate GCSE Computer Science Textbook (c) 2018

Cycle 2 The clock can now tick again for the next fetch-execute cycle (c) 2018

Fetch stage - 1 CPU RAM (c) 2018 Address Bus C U Data Bus A L U The address in memory of the next instruction is already stored in the Program Counter (PC) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4 25  5 12  6 M A R 4 P C - Data Bus 1 C U M D R 25 C I R LOAD 4 A L U Control Bus A C C 25 (c) 2018

Fetch stage - 2 CPU RAM (c) 2018 The address in the Program Counter (PC) is copied to the Memory Address Register (MAR) The Control Unit sends the contents of the Memory Address Register to RAM RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4 25  5 12  6 M A R 4 P C - Data Bus 1 C U M D R 25 C I R LOAD 4 A L U Control Bus A C C 25 (c) 2018

Fetch stage - 3 CPU RAM (c) 2018 Address Bus C U Data Bus A L U The instruction is now retrieved from memory and sent along the data bus to the Memory Data Register (MDR) The instruction is then copied from the Memory Data Register (MDR) to the Current Instruction Register (CIR) Finally the value of the Program Counter is increased by one ready for the next instruction after the fetch execute cycle RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4 25  5 12  6 M A R - P C - Data Bus 1 1 2 C U ADD 5 M D R - C I R LOAD 4 ADD 5 A L U Control Bus A C C 25 (c) 2018

Decode stage CPU RAM (c) 2018 The instruction in the Memory Data Register (MDR) is decoded by the Control Unit (CU) add is recognised as the op-code (instruction) and 5 as the operand (memory location) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4 25  5 12  6 M A R - P C - Data Bus 1 2 C U M D R - C I R - ADD 5 ADD 5 ADD 5 A L U Control Bus A C C 25 (c) 2018

Execute stage - 1 CPU RAM (c) 2018 The memory address is copied from the CIR to the Memory Address Register (MAR) It is then passed along the address bus to main memory (RAM) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4 25  5 12  6 M A R - P C - Data Bus 1 5 2 C U M D R - C I R - LOAD 4 ADD 5 5 A L U Control Bus A C C 25 (c) 2018

Execute stage - 2 CPU RAM (c) 2018 The data at that memory address is passed to the Memory Data Register (MDR) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4  25  5 12  6 M A R - P C - Data Bus 5 2 C U M D R - C I R - ADD 5 ADD 5 A L U Control Bus A C C 25 5 12 (c) 2018

Execute stage - 3 CPU RAM (c) 2018 Address Bus C U Data Bus A L U The instruction from the Current Instruction Register is then executed on the data in the MDR In this example, 12 is added from the Memory Data Register (MDR) to the Accumulator (ACC) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4 25  5 12  6 M A R - P C - Data Bus 5 2 C U M D R - C I R ADD 5 12 12 ADD 5 ADD A L U Control Bus A C C 25 25 (c) 2018

Execute stage - 4 CPU RAM (c) 2018 The calculation is carried out by the Arithmetic Logic Unit (ALU) The result of the calculation is stored in the Accumulator (ACU) RAM   CPU   Address Bus Address Contents  0 LOAD 4  1 ADD 5  2    3  4 25  5 12  6 M A R - P C - Data Bus 5 2 C U M D R - C I R ADD 5 12 ADD 5 A L U Control Bus A C C 25 25 37 12 ADD (c) 2018

Textbook reading Read pages 11-14 of Chapter 1 – Computer Systems from The Ultimate GCSE Computer Science Textbook (c) 2018

Activity – fetch-execute cycle When prompted, click on “I recognise this content” Follow this animation from www.tiny.cc/fetchexecuteanimation (requires flash)

Activity – fetch-execute cycle Complete question 2 of the activity on the fetch-execute cycle from The Ultimate GCSE Computer Science Textbook (c) 2018

Performance of the CPU (c) 2018

Performance of the CPU (c) 2018 Performance Cache Type Performance Factors affecting performance of the CPU include: Clock speed Number of processor cores Cache size Cache type Cache Size Cores Clock Speed (c) 2018

Textbook reading Read pages 16-18 of Chapter 1 – Computer Systems from The Ultimate GCSE Computer Science Textbook (c) 2018

Clock speed (c) 2018 Number of clock cycles per second Measured in Hz eg 3 GHz (gigahertz) = 3 billion ticks per second more ticks = more instructions per second Overclocking Increasing CPU speed in the BIOS Can cause overheating Some processes may not complete before next instruction starts Results in corrupted data (c) 2018

http://tiny.cc/cpuperformance - factors beyond CPU Clock Speeds that affect Performance

Number of processor cores Core = processing unit which receives instructions and performs calculations More cores do not make the processor faster More cores do allow more instructions to run at the same time BUT only if a program or operating system support it Performance will improve through: parallel processing multitasking Term Number of cores Single-core 1 Dual-core 2 Quad-core 4 Octa-core 8 Tip: avoid using number of cores as an answer in an exam (c) 2018

Parallel processing and multi-tasking different instructions from the same program run at the same time more cores = more instructions from the same program running at the same time Multitasking instructions from many programs run at the same time more cores = more instructions from many programs running at the same time 7 1 6 9 4 5 3 2 8 (c) 2018

Single core processor (c) 2018 Instructions happen one at a time in sequence for 1 Hz, this would be up to 1 instruction every second: 8 7 9 1 6 4 2 3 5 (c) 2018

Dual core processor (c) 2018 With a multitasking operating system or software that supports parallel processing: two instructions can be run in parallel at a time for 1 Hz, this would be up to 2 instructions per second: what happened with the 9th instruction? 7 1 9 5 3 Answers to the question could include: It was the last instruction with no more left It was different software that doesn’t support parallel processing 2 8 4 6 (c) 2018

Quad core processor (c) 2018 8 7 9 1 6 4 2 3 5 We already know: with a multitasking operating system or software that supports parallel processing: two instructions can be run in parallel at a time for 1 Hz, this would be up to 2 instructions per second BUT without a multitasking operating system or without software that supports parallel processing: only one core will be used for 1 Hz, this would be up to 1 instruction every second, not 4 instructions per second: 8 7 9 1 6 4 2 3 5 (c) 2018

http://tiny.cc/cores - How the Number of Cores affects Performance

Cache (c) 2018 Super fast memory Built into the CPU Stores recently used instructions Improves performance because: frequently used instructions can be retrieved from cache instead of RAM eg: the instructions in a loop will be stored in cache cache can be accessed more quickly than RAM (c) 2018

Cache example (c) 2018 Main Memory CACHE CPU print(“Start of loop”) for i = 1 to 5 print(“Hello“) end for print(“End of loop”) New instructions are retrieved from memory If they are in the cache, they are retrieved directly from cache print(“Hello”) print(“Hello”) CACHE print(“End of loop”) print(“End of loop”) print(“Start of loop”) print(“Hello”) print(“Hello”) print(“Hello”) print(“Hello”) print(“Hello”) CPU print(“End of loop”) (c) 2018

Levels of cache - 1 (c) 2018 3 Levels of cache Level 1 is closest to CPU Level 3 is furthest away from CPU Level 1 stores most frequently used instructions (c) 2018

Levels of cache - 2 When Level 1 is full, Level 2 will be used When Level 2 is full, Level 3 will be used Most frequently used instructions are stored Level 1 Level Part of CPU Access Time Distance from CPU Size 1 Yes Fastest Closest Smallest 2 Can be Medium Middle 3 No Slowest but faster than RAM Furthest Largest (c) 2018

http://tiny.cc/cachememory - What Cache Does

http://tiny.cc/cacheperformance - How Cache affects Performance

Cache effect on performance of CPU More cache = faster performance Closer level of cache = faster performance (c) 2018

Questions YOUR TURN! (c) 2018 Answer the questions on pages 18 and 19 of The Ultimate GCSE Computer Science Textbook (c) 2018