Statistical Analysis and Design: From Picoseconds to Probabilities Chandu Visweswariah IBM Thomas J. Watson Research Center Yorktown Heights, NY http://www.research.ibm.com/people/c/chandu With acknowledgments to the extended timing, modeling, synthesis and methodology teams at IBM Yorktown, Fishkill and Burlington First of all, I would like to thank the organizers of this conference for inviting me to this beautiful part of this beautiful country to give a tutorial. My thanks in particular are due to (a) Prof. Guido Araujo of IC-UNICAMP, (b) Prof. Edna Barros of Recife and (c) Dr. Reinaldo Bergamaschi of IBM Research. The topic of today’s tutorial is a relatively new topic, that of statistical timing. I will attempt to introduce this material to you in a gentle and systematic manner. Please feel free to ask questions at any time; I will also pause after each section to give you a chance to ask questions. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Happy Independence Day! Speaking of a beautiful country, I would like to take this opportunity to wish Brazil and all the Brazilians in the audience a very HAPPY INDEPENDENCE DAY! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Propositions (and outline) Variability is proportionately increasing; therefore, a new paradigm is required Correlations matter Statistical timing tools are rising to the challenge Robustness is an important metric Statistical treatment of variability will pervade all aspects of chip design methodology, manufacturing and test ASICs and processors will both benefit Here is an outline of my talk. Q1: What is new? Q2: What is the unique characteristic of this problem? Q3: Can we handle it? Q4: Does it bring new metrics to the table? Q5: Does it require new methodologies? For ASICs? Processors? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Section 1: The Problem … and what exactly is a statistical timer? PAUSE FOR QUESTIONS! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

The march of technology Performance Is this worth a huge investment? Technology generation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

The source of the problem Variability is proportionately increasing manufacturing FEOL: critical dimensions are scaling faster than our control of them BEOL: variability dramatically increases the number of independent and significant sources of variation environmental (Vdd, temperature) fatigue (NBTI, hot electron effect) across-chip (OCV/ACLV, temperature, Vdd) circuit design (PLL jitter, coupling noise, SOI history) model-to-hardware correlation OCV = On-chip Variation (Synopsys term) ACLV = Across-chip linewidth variation (IBM term) Note that unknowns can be modeled as random variables! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Delay impact of variations Parameter Delay Impact BEOL metal (Metal mistrack, thin/thick wires) -10% → +25% Environmental (Voltage islands, IR drop, temperature) 15 % Device fatigue (NBTI, hot electron effects) 10% Vt and Tox device family tracking (Can have multiple Vt and Tox device families)  5% Model/hardware uncertainty (Per cell type) N/P mistrack (Fast rise/slow fall, fast fall/slow rise) PLL (Jitter, duty cycle, phase error) These numbers are qualitative. The main point is the sentence at the bottom of the slide. [Courtesy Kerim Kalafala] Requires 220 timing runs or [-65%,+80%] guard band! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Can you answer these questions about your favorite digital chip? What does 5% random delay variability on each gate and wire do to your frequency distribution? What does 5% correlated delay variability do to your frequency distribution? What % delay variation leads to a hold violation? How many yield points does OCV/ACLV cost? What is the shape of your parametric yield curve? What is the sensitivity of your chip’s frequency to thickness of a metal level? gate/wire mistracking? N/P mistracking? mistracking between metal levels i and j? These are relatively simple and straightforward questions that we cannot answer today. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities New paradigm required ASICs old paradigm: sign-off is corner- or case-based would require 220 timing runs to hit all corners cumbersome, risky and pessimistic all at the same time! Microprocessors for the most part, nominal performance is targeted some ad hoc methods to deal with certain types of mistracking Both our design/synthesis methods do not target robustness, nor do our timing tools measure robustness or give credit for robust design Solution: statistical timing and optimization © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities ITRS predictions © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Even so noteworthy, noble and accurate a journalistic venture as EE Times agrees with us! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities … the big splash came not from a commercial EDA company but from IBM Corp. All right, enough… what is all this hype about? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

What is a statistical timer? Static timer Delay and slew models Netlist + assertions 1. Slack 2. Diagnostics Statistics of the sources of variability Dependence on sources 1. Yield curve 2. Diagnostics Statistical timer © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Parametric yield curve $$ $ ¢¢ ¢ Yield We will leave it here. The goal of a statistical timer is to predict the parametric yield curve, and to offer diagnostics to improve the parametric yield curve. In the next two sections, we will study the nature of the problem (we will find that it is a multi-million variable multi-variate correlated probability problem) and how to solve it. Clock frequency © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Section 2: The Importance of Correlations … and why they make computations a pain PAUSE FOR QUESTIONS! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Importance of correlations Consider a circuit with 50K latches, each with a setup and hold test, each of which has a 99.99% probability of being met If all tests are perfectly correlated, yield = 99.99% If all tests are perfectly independent, yield = 0.005% The truth is closer to the perfectly correlated case! Luckily… © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Correlation due to path sharing © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Clock and cell-type correlation Stress the “launching path/capturing path” or “data path/clock path” paradigm. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Voltage island correlation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Global correlation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Temperature/Vdd correlation © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Geographical correlation Note that a reticle field is typically 4 chips. [From M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, ICCAD 2000] © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Types of variability Global within a die/reticle metal dimensions device family strength mistracking ambient temperature and power supply Spatial/local correlation across a die/reticle Leff junction temperature, Vdd Independently random tox doping effects © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

First-cut approach to static timing Deterministic a b c + MAX Statistical b a c + MAX Question: what do correlations do to the MAX and PLUS operations? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

The max of two unit Gaussians Probability  Note!      Correlation is good! Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Equally critical signals (=0) Probability 1 2 3 30 Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Equally critical signals (=0.5) Probability 1 2 3 30 Correlation is good! Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Equally critical signals (=1.0) Probability 1 2 3 30 Correlation is good! Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Thirty equally critical signals Probability =1 =0.5 =0 To summarize the last 3 figures… Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Slack histogram untuned tuned uncertainty- aware tuned #paths +20 ps slack © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

The sum of n unit Gaussians (=1.0) Probability 1 Gaussian: -3 to 3; 2 Gaussians: -6 to +6; n Gaussians: -3n to +3n, so -30 to +30 for last curve. Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

The sum of n unit Gaussians (=0.5) Probability Spread is tighter! Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

The sum of n unit Gaussians (=0) Probability 1 Guassian: -3 to 3; 2 Gaussians: -3sqrt(2) to +3sqrt(2) which is -4.2 to +4.2; n Gaussians: -3sqrt(n) to 3 sqrt(n), so the last curve is -10 to 10. Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Summary: the sum of 10 unit Gaussians Probability    Delay © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Conventional wisdom revisited Conventional wisdom says, “Use sizing and multiple Vts to tune the circuit aggressively, creating a wall of critical paths the new wisdom is to optimize the expected value of the critical path delay, which in turn means reducing the wall of critical paths Conventional wisdom says, “Make pipeline stages short and crank up clock frequency” the new wisdom is to take advantage of RMS/ RSS effects in moderately longer pipelines © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Separating out independent randomness New: systematic variability N(20,2/3) Old: N(20,1) New: independent variability N(0,1/3) © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Case study Consider a critical path of 50 identical gates Old: assume delay of each gate is N(20,1) ps (corner delays are 17 and 23 ps) New: assume delay of each gate is N(20,2/3) ps + N(0,1/3) ps (same corner delays) Old: critical path delay (3) = 2350 = 1150 ps New: critical path delay (3) = 2250 + 31/350 = 1100 + 7.1 = 1107.1 Improvement in critical path delay = 3.7% This case study can be generalized © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Generalization of case study Skip the math.! As N↑, the benefit ↑ As v↑, the benefit ↑ As f↑, the benefit ↑ Rule of thumb: for 50 stages and 5% variability (), each percent of independent variability buys 0.1% of critical path delay improvement © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Plot of benefit for N=50 For 50 stages of logic and 5% variability, the benefit is 3.7%. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

What about shorter paths (=5%)? For 35% fraction of independent variability, the benefit falls off from 3.7% to about 3% due to short paths. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

M equally critical paths Basic issue suppose there are M equally critical paths each of these paths has already received RMS credit, so the delay of each path consists of a constant which is the nominal/intrinsic delay of the path plus the corner-based systematic variability an independent variability part for which we have received an RMS credit, so there is a small probability that the delay is beyond the 3 limit with a large number of equally critical paths, the 3 of the MAX delay of all M paths is not equal to the 3 delay of each of the M paths question: how big is this sigma shift? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities A little analysis Skip the math.! Example: with M=50, we have to use a 4.037 value on the random part instead of 3 to get a “true 3” delay on the maximum delay of 50 paths; this diminishes RSS credit The benefit after taking this into account is plotted in general versus M and N on the next page, assuming f=1/3, v=5% © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Benefit of RMS credit + equally crit. paths The 3.7% credit that we started with degrades to just under 3% due to 1,000 critical paths. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical timing experiment Arrival time=0 Data Latch with zero setup guard time Clock N(10,1) Arrival time=0 How will slack change with ? © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Timing experiment result Probability =1 =0.5 =0 Final message: correlation is a good thing! Slack © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

There’s no question: correlation’s a pain Of neat math. formulas, it’s the bain! Though your timer becomes a morass It’s correlation that saves your … (chip) © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Section 3: Statistical Timing Tools … can they rise to the challenge? PAUSE FOR QUESTIONS! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical timing tools Path-based conduct a nominal timing analysis list a representative set of critical paths (question: how may paths? question: which paths?) model the delay/slack of each path as a function of random variables (the underlying sources of variation) predict the parametric yield curve (statistical MIN of all path slacks), as well as generate diagnostics Block-based propagate arrival times and required arrival times in the form of probability distributions linear time approximate, quick-and-dirty © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical timing tools © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Feasible region in parameter-space Yield improvement or line-tailoring vector Feasible region JPDF of global parameters Integration of the JPDF over the feasible region is the parametric yield © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Path-based statistical timing © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Block-based statistical timing Deterministic Statistical a b c + MAX b a c + MAX © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Canonical variational delay model Correlations are the problem in a circuit with 1M nodes and 2M edges and 12 timing values per node/edge, we DO NOT want to store or manipulate a 36M x 36M covariance matrix! instead, parameterize all timing quantities by the sources of variation first-order canonical model: Constant (nominal value) Sensitivities Deviation of global sources of variation from their nominal values Random uncertainty (deviation from nominal value) © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Procedure Express all delays, slews, arrival times, required arrival times and slacks in canonical form Propagate arrival times forward through the timing graph while preserving correlations Propagate required arrival times backward while preserving correlations Slack is the difference of arrival and required arrival times Each path, node and edge has a probability of being critical; these criticality probabilities can be computed easily All results are also available in canonical form; these diagnostics are extremely useful! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Interpreting statistical timing results Critical path is not unique Critical paths can be listed in order of probability of being critical this should be the order in which the timing of paths is “fixed” or optimized In deterministic timing, slack is identical along the critical path This property does not hold in the case of statistical timing Slacks reflect not only timing shortfalls, but also robustness shortfalls © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Latch timing considerations Probability Data arrival time Clock arrival time © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Sample comparison to Monte Carlo Block-based statistical timer, 18 seconds CPU time Monte Carlo, 14 hours CPU time Test chip (3K gates) © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Overhead of statistical calculations Run time overhead about 20% on batch operation about 50% on the actual arrival time propagation Memory overhead about 100% depending on the number of sources of variation and complexity of the models Capacity able to time 2M+ gate ASIC chips on 64-bit machines Note: you will hopefully replace several static timing runs by a single statistical timing analysis. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Methods of handling ACLV/OCV ACLV/OCV is traditionally handled by heuristic derating coefficients an early/late delay split is applied, and late data is compared to early clock and vice versa However, we want to give credit to compactly laid out launching/capturing path pairs and penalize path pairs that snake all over the chip By taking advantage of spatial correlation, we can obtain proximity credit © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Path-based solution The setup and hold test can be penalized by an early/late split based on the size of this bounding box © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Block-based solution #1 From A. Agarwal et al, TAU ’02 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Block-based solution #2 From H. Chang et al, ICCAD ’03 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Section 4: Robust Design … sure, the process is all over the place, but can I use design techniques to attenuate the effect? PAUSE FOR QUESTIONS! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Remember these? In addition to correctness, power, signal integrity and area, please welcome robustness to variation as a first-class design metric © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Robust design First order model Tremendously valuable if the statistical timer produces timing results in 1st order canonical form: Constant (nominal part) Sensitivities Global variations Random uncertainty © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Opportunities for robust design Find out which sources of variation are the biggest yield detractors; quantify robustness of a design Any commonality between data and clock cancels out to first order voltage islands, gate types, device types, metal levels used for interconnect, proximity of launching and capturing paths Robustness-enhancing design decisions high sensitivity to N/P mistrack  resynthesize with fewer tall P stacks, for example high sensitivity to a particular metal level  re-route high sensitivity to Vt mistrack  try to balance use of low/high Vt devices in capturing and launching paths high sensitivity to wire/gate mistrack  try to rebalance delay Producing timing results in canonical form can help with line tailoring © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

How synthesis techniques will evolve Phase 1 true 3 timing sign-off with statistical timing Phase 2 use statistical timing to guide the physical synthesis and routing optimization (implicit robustness credit) Phase 3 further reduce performance  by actively targeting robustness (explicit robustness credit) Phase 4 with the mainstream availability of at-speed test, enable yield/performance tradeoffs I will talk about the difference between true 3 sigma sign-off and corner-based sign-off in tomorrow’s panel. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Section 5: Methodology … will ASICs benefit? processors? PAUSE FOR QUESTIONS! © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

ASICs vs. microprocessors We will next compare and contrast corner-based methods with statistical methods. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Check front-end corners: possible escapes 1 2 3 -3 -2 -1 BEOL 800 MHz 900 MHz FEOL 1 GHz © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities 600 MHz Check all corners: no escapes, pessimistic 1 2 3 -3 -2 -1 BEOL 800 MHz 900 MHz FEOL 1 GHz © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities 600 MHz Statistical timing: no escapes, less pessimism 1 2 3 -3 -2 -1 BEOL 700 MHz 800 MHz 900 MHz FEOL 1 GHz © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

ASIC timing methodology Checking “all corners” is very pessimistic Checking “all corners” is intractable Statistical timing fits in “naturally” With the same area/power targets and the same tool suite, but a statistical timer to guide the placement, routing and optimization, the estimated performance improvement is of the order of 20% in 90nm technology Test coverage can be improved by exploiting statistical timing results With at-speed test, arbitrary performance vs. yield tradeoffs can be made based on business needs © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

MHC, line tailoring Good chips Path report file with criticality probabilities + process coverage Canonical variational delay model Statistical timing Technology characterization + delay model generation Test vector generation At-speed test Bad chips with failing path signatures Path sensitivities Correlation analysis and diagnosis Model-to-hardware correlation and/or line tailoring MHC, line tailoring © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Possible microprocessor methodology Individual macros Robustness budget Assertions Statistical timing for optimization “Sign-off” statistical timing and abstraction Global wires Other macros Unit or chip-level statistical timing for optimization Unit or chip-level statistical “sign-off” timing (Mostly) FEOL variability models (Mostly) BEOL variability models Update timing and robustness budgets © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Vt variations Probability Good chips Too slow Too leaky Vt Requires simultaneous power/timing sign-off © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Section 6: Propositions And now to conclude, let me state again the propositions of this presentation. © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Propositions Variability is proportionately increasing; therefore, a new paradigm is required Correlations matter Statistical timing tools are rising to the challenge Robustness is an important metric Statistical treatment of variability will pervade all aspects of chip design and manufacturing ASICs and processors will both benefit © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities

Statistical Analysis and Design: From Picoseconds to Probabilities Quotable quotes* Statistical thinking will one day be as necessary for efficient (chip-design) citizenship as the ability to read and write. -- H. G. Wells There are three kinds of lies: lies, damned lies and statistics. -- Disraeli It ain’t so much the things we don’t know that get us in trouble. It’s the things we know that ain’t so. -- Artemus Ward Round numbers are always false. -- Samuel Johnson I will be happy to take questions, and in the meanwhile, here are some quotations to amuse you. Thank you. *From “How to Lie with Statistics,” by Darrell Huff, Norton, 1954 © Chandu Visweswariah, 2004 Statistical Analysis and Design: From Picoseconds to Probabilities