External Read Cycle How fast does The RAM have to Be? 7 osc. Cycles

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Presentation transcript:

External Read Cycle How fast does The RAM have to Be? 7 osc. Cycles Recall design Of P0: active pullup And pulldown so Data bus can “float”

External Write Cycle Multiplex data and Low address on P0 (destroys value on P0) P2 used for high byte, returns To port value after use.

Access to External RAM In software (always through indirect addressing) MOV R0, #external_address MOVX A,@RI # uses only 8-bit address for external RAM Or MOV DPL, #external_address_high MOV DPH, #external_address_low MOVX A, @DPTR; Yet another address space (declare as xdata or pdata)

Circuit for external Data Mem.? !(P2_7) ? 8051 7 RAM (32K x 8) P2 A[14:8] \CE \RD \RE \WR \WR ? ALE Latch 8 8 P0 A[7:0] D[7:0] 8

Memory Mapped I/O LCD Display 2 lines x 16 characters A[ : ]? D[7:0] \CE \E Digital Sensor Array 8051 PLD P2 P0 ctl RAM 32K x 8 A D

Programming the PLD