The Impact of Aging on FPGAs Instructor : Shing-Min Liu Students : 607410061 蔣宗廷; 607410130 林子淵

Degradation in Contemporary FPGAs A modern VLSI circuit, under normal conditions, can be expected to operate continuously for several years before any significant degradation becomes apparent, so the aging process was accelerated with a combination of elevated voltage and temperature.

Design Concept of Degradation FPGAs The experiment has two main components A means of measuring the timing performance of test circuits A means of inducing degradation

Principle of the Measurement Method A delay measurement method based on transition probability (TP), proposed in [1], has three major advantages: It is able to measure the delay of key configurable components such as interconnects, LUTs and registers. The test circuit itself is robust against timing failure; measurement accuracy is largely independent from degradation in the test circuitries. Circuits under test (CUTs) are constructed from normal logic paths and are representative of real designs. J. S. J. Wong, P. Sedcole, and P. Y. K. Cheung. “A transition probability based delay measurement method for arbitrary circuits on FPGAs” In Int. Conf. on Field Programmable Tech., pages 105–112, 2008. [1]

Accelerated-Life Conditions Voltage is the strongest accelerator of ageing; in NBTI, the dominant mechanism observed, the voltage dependence is approximately 𝑡 𝑓 ∝ V 𝑔𝑠 −𝛾 [2]. The second external acceleration factor was temperature. Here, the influence on NBTI follows a common Arrhenius law of 𝑡 𝑓 ∝ exp 𝐸 𝛼 κ𝑇 [2]. X. Li et al. “Compact modeling of MOSFET wearout mechanisms for circuit reliability simulation.” IEEE Trans. Device Mat. Rel., 8(1), Mar. 2008. [2]

Issues of Aging uncertainties involved with the severe acceleration of aging. quantify the lifetime of an FPGA is difficult. Was the FPGA stable and functioned normally under a 1V increase in core supply voltage? The issues may cause severe problems. For example, Elevated voltage increases power dissipation and the likelihood of breakdown.

Conclusion Nor, given the uncertainties involved with the severe acceleration of ageing, did we expect to quantify the lifetime of an FPGA. It was important to limit the increase to avoid rapid catastrophic failure.