Introduction EE4271 VLSI Design Professor Shiyan Hu Office: EERC 518 shiyan@mtu.edu Introduction Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

Class Time and Office Hour Class Time: MWF 16:05-16:55 (EERC 214) Office Hours: MWF 15:00-16:00 or by appointment, office: EERC 518 Textbook (required): Digital Integrated Circuits: A Design Perspective, second edition, by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Prentice Hall, 2003. or CMOS VLSI Design: A Circuits and Systems Perspective, fourth edition, by Neil H.E. Weste and David M. Harris, Addiuson Wesley, 2009 Grading: Homework 20% Midterm 20% Final 30% Lab 30%

Course Website http://www.ece.mtu.edu/faculty/shiyan/EE4271Fall16.htm Contact information of instructor Professor Shiyan Hu Email: shiyan@mtu.edu EERC 518 Instructor’s webpage: http://www.ece.mtu.edu/faculty/shiyan

What is this course all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Combinatorial Circuits and Sequential circuits. Computer-Aided Design. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: speed, power dissipation, cost, and reliability

Agenda Introduction: Issues in digital integrated circuit (IC) design Device: MOS Transistors Wire: R, L and C Fabrication process CMOS inverter Combinational logic structures Sequential logic gates Design methodologies VLSI Computer-Aided Design Timing/power optimizations on gate and interconnect

Introduction Why is designing digital ICs different today than it was before? What is the challenge?

The Transistor Revolution First transistor Bell Labs, 1948

The First Integrated Circuit First IC Jack Kilby Texas Instruments 1958

Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation

Intel 8080 Micro-Processor 1974 4500 transistors

Intel Pentium (IV) microprocessor 2000 42 million transistors 1.5 GHz

Modern Chip

Moore’s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

Moore’s law Twice the number of transistors, approximately every two years

Moore’s Law Electronics, April 19, 1965.

Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000 Pentium® III 10,000 Pentium® II Pentium® Pro 1,000 Pentium® i486 i386 100 80286 10 8086 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Courtesy, Intel

ITRS Prediction 17

Moore’s law in Microprocessors 1000 2X growth in 1.96 years! 100 10 P6 Pentium® proc Transistors (MT) 1 486 386 0.1 286 Transistors on Lead Microprocessors double every 2 years 8086 8085 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Courtesy, Intel

Lead Microprocessors frequency doubles every 2 years Not true any more! 10000 Doubles every 2 years 1000 P6 100 Pentium ® proc Frequency (Mhz) 486 10 386 8085 8086 286 1 8080 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel

Interconnects Dominate 300 250 200 Interconnect delay 150 Delay (psec) 100 Transistor/Gate delay 50 20 [CF] The problem is that at 0.18u and below interconnect overwhelmingly dominates the delay on a chip, and current design methods have been created to only consider the delay from the transistor gate. So, you never get a true timing picture of the performance of your chip during your design iterations. The impact of this is difficulty in achieving Design Closure. This is important because it will cause delay in the delivery of your chip and uncertainty in its performance. [Michel] The above graphic shows how interconnect delay accounts for most of the delay in chips today and will continue to do so with advancing technologies. This is mainly due to the shrinking gate sizes which reduces the gate capacitance and the shrinking widths and spacing of the interconnect which increases the overall interconnect capacitance. Please turn to the next slide titled “and Coupling Dominates Interconnect”. 0.8 0.5 0.35 0.25 0.25 0.18 0.15 Technology generation (m) Source: Gordon Moore, Chairman Emeritus, Intel Corp. 20 20

Lead Microprocessors power continues to increase Power Dissipation 100 P6 Pentium ® proc 10 486 286 Power (Watts) 8086 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power continues to increase Courtesy, Intel

Power is a major problem 100000 18KW 5KW 10000 1.5KW 1000 500W Pentium® proc Power (Watts) 100 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power delivery and dissipation will be prohibitive Courtesy, Intel

Power density too high to keep junctions at low temp 10000 Rocket Nozzle 1000 Nuclear Reactor Power Density (W/cm2) 100 8086 10 Hot Plate 4004 P6 8008 8085 386 Pentium® proc 286 486 8080 1 1970 1980 1990 2000 2010 Year Power density too high to keep junctions at low temp Courtesy, Intel

Not Only Microprocessors Analog Baseband Digital Baseband (DSP + MCU) Power Management Small Signal RF RF Cell Phone Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 Units 48M 86M 162M 260M 435M (data from Texas Instruments)

Many Chips 25

Challenges in Digital Design • Ultra-high speed design Interconnect delay • Reliability, Manufacturability • Power Dissipation • Time to market

Complexity outpaces design productivity Productivity Trends Logic Transistor per Chip (M) 10,000,000 10,000 1,000 100 10 1 0.1 0.01 0.001 100,000,000 0.01 0.1 1 10 100 1,000 10,000 100,000 Logic Tr./Chip 1,000,000 10,000,000 Tr./Staff Month. 100,000 1,000,000 Complexity 58%/Yr. compounded 10,000 (K) Trans./Staff - Mo. Productivity 100,000 Complexity growth rate 1,000 10,000 x x 100 1,000 x x 21%/Yr. compound x x x Productivity growth rate x 10 100 1 10 2003 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2005 2007 2009 Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap

Computer-Aided Design Every new generation can integrate 2x more functions per chip Chip price does not increase significantly Cost of a function decreases by 2x However, Design engineering population does not double every two years. How to design much more complex chips (with more and more functions)? Great need for ultra-fast design methods Design Automation (Computer-Aided Design)

Design Abstraction Enables CAD SYSTEM MODULE + GATE CIRCUIT DEVICE G S D n+ n+

Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Speed (delay, operating frequency) Power dissipation Cost Design time Design effort Reliability Process, voltage and temperature variations

Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort to design layout and mask one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area

NRE Cost is Increasing

Die Cost Single die Wafer Going up to 12” (30cm) From http://www.amd.com

Yield

Defects is approximately 3 in the current fabrication process About 0.5-1 defect per cm2.

Some Examples (1994) Chip Metal layers Line width Wafer cost Def./ cm2 Area mm2 Dies/wafer Yield Die cost 386DX 2 0.90 $900 1.0 43 360 71% $4 486 DX2 3 0.80 $1200 81 181 54% $12 Power PC 601 4 $1700 1.3 121 115 28% $53 HP PA 7100 $1300 196 66 27% $73 DEC Alpha 0.70 $1500 1.2 234 53 19% $149 Super Sparc 1.6 256 48 13% $272 Pentium 1.5 296 40 9% $417

Summary Digital integrated circuit design faces huge challenges for the coming decades High speed Low power Short design time for highly complex circuit having 1 billion transistors Reliable under noise and variations Purpose of the course Understand the basics of VLSI design Getting a clear perspective on the challenges and potential solutions