ESS BCM Firmware 1.

Slides:



Advertisements
Similar presentations
Digital RF Stabilization System Based on MicroTCA Technology - Libera LLRF Robert Černe May 2010, RT10, Lisboa
Advertisements

26-Sep-11 1 New xTCA Developments at SLAC CERN xTCA for Physics Interest Group Sept 26, 2011 Ray Larsen SLAC National Accelerator Laboratory New xTCA Developments.
29 April 2005 Part B Final Presentation Peripheral Devices For ML310 Board Project name : Spring Semester 2005 Final Presentation Presenting : Erez Cohen.
General Purpose FIFO on Virtex-6 FPGA ML605 board midterm presentation
FT-UNSHADES2. H.G. Miranda, M.A. Aguirre, J. Barrientos, L. Sanz Electronic Engineering Dpt. School of Engineering. University of Sevilla (SPAIN) Sevilla,
Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf
General Purpose FIFO on Virtex-6 FPGA ML605 board Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf 1 Semester: spring 2012.
UCT Software-Defined Radio Research Group
Wir schaffen Wissen – heute für morgen 24 August 2015PSI,24 August 2015PSI, Paul Scherrer Institut Status WP 8.2 RF Low Level Electronic Manuel Brönnimann.
PCIe Mezzanine Carrier Pablo Alvarez BE/CO. Functional Specifications External Interfaces User (application) FPGA System FPGA Memory blocks Mezzanine.
XTCA activities at CERN Markus Joos PH-ESE xTCA interest group – Background – Report of the 2 nd meeting (held on 7.3.) uTCA evaluation and AMC development.
Pulsar II Hardware Overview Jamieson Olsen, Fermilab 14 April 2014
DAQ Link integration update A Navarro Tobar*, JM Cela Ruiz 10/2/2015.
Slide ‹Nr.› l © 2015 CommAgility & N.A.T. GmbH l All trademarks and logos are property of their respective holders CommAgility and N.A.T. CERN/HPC workshop.
DDRIII BASED GENERAL PURPOSE FIFO ON VIRTEX-6 FPGA ML605 BOARD PART B PRESENTATION STUDENTS: OLEG KORENEV EUGENE REZNIK SUPERVISOR: ROLF HILGENDORF 1 Semester:
VC707 Evaluation Kit Xilinx Virtex-7 In_0 GTX MHz IDELAY 8B/10B Serilizer 7 0 7IDELAY 0=>K28.5 0=>K28.1 D(15:0) K(1:0) 8B/10B IDELAYCTRL LHC_Clk.
Genova May 2013 Diego Real – David Calvo IFIC (CSIC – Universidad de Valencia) CLBv2 1.
Sumary of the LKr WG R. Fantechi 31/8/2012. SLM readout restart First goal – Test the same configuration as in 2010 (rack TS) – All old power supplies.
ATCA based LLRF system design review DESY Control servers for ATCA based LLRF system Piotr Pucyk - DESY, Warsaw University of Technology Jaroslaw.
Mitglied der Helmholtz-Gemeinschaft Status of the MicroTCA developments for the PANDA MVD Harald Kleines, ZEL, Forschungszentrum Jülich.
E. Hazen1 MicroTCA for HCAL and CMS Review / Status E. Hazen - Boston University for the CMS Collaboration.
E. Hazen -- ACES ACES 2011 MicroTCA in CMS E. Hazen, Boston University for the CMS collaboration.
E. Hazen -- Upgrade Week1 AMC13 Project Status E. Hazen - Boston University for the CMS Collaboration.
E. Hazen -- xTCA IG1 AMC13 Project Status E. Hazen - Boston University for the CMS Collaboration.
E. Hazen1 AMC13 Project Status E. Hazen - Boston University for the CMS Collaboration.
Creotech Instruments Jacek Kosiec On behalf of.
Counting Room Electronics for the PANDA MVD
OTMB Development and Upgrade Plan for LS2
JESD204B High Speed ADC Interface Standard
Use of FPGA for dataflow Filippo Costa ALICE O2 CERN
AMC13 Project Status E. Hazen - Boston University
The Jülich Digital Readout System for PANDA Developments
DAQ and TTC Integration For MicroTCA in CMS
The SLAC Instrumentation and Control Platform
Test Boards Design for LTDB
AMC13 T1 Rev 2 Preliminary Design Review E. Hazen Boston University
Pulsar 2b AMchip05-based Pattern Recognition Mezzanine
E. Hazen - Back-End Report
LIU – SPS Low level RF Updates and schedule G. Hagmann,
- PANDA EMC Readout System
AMC13 Status Report AMC13 Update.
Production Firmware - status Components TOTFED - status
Electronics for MEG-II
Erno DAVID, Tivadar KISS Wigner Research Center for Physics (HU)
The Train Builder Data Acquisition System for the European-XFEL
The ELENA BPM System. Status and Plans.
FrontEnd LInk eXchange
LATOME LAPP Nicolas Dumont Dayot on behalf of the LAPP team
FMC adapter status Luis Miguel Jara Casas 5/09/2017.
MicroTCA Common Platform For CMS Working Group
GBT-FPGA Interface Carson Teale.
MULTIBOOT AND SPI FLASH MEMORY
Development of new CN for PXD DAQ
2nd MTCA Workshop for Industry and Research
ChipScope Pro Software
ChipScope Pro Software
Plan for controls with the digital platform
Risk, Schedule, Deliveries
Safety, reliability and maintainability
Digital platform for nBLM
Implementation of nBLM algorithms on IOxOS IFC 1410
ICS platforms for beam instrumentation
Control Systems for the APTM and GRID
Clement Derrez European Spallation Source ERIC Date
CON-FMC Connect any computer to FPGA through USB June 2019
LIU BWS Firmware status
Kaj Rosengren FPGA Designer – Beam Diagnostics
TTC setup at MSU 6U VME-64 TTC Crate: TTC clock signal is
Firmware implementation at ESS
Presentation transcript:

ESS BCM Firmware 1

ESS BCM FIRMWARE ESS platform migration BCM Optical link ESS DEVENV for IKCs

ESS BCM FIRMWARE ESS platform migration BPM Optical link ESS DEVENV for IKCs

MTCA.4 AMC MIGRATION BEAM DIAGNOSTIC PLATFORM STRUCK SIS8300L2 + SIS8900 MIGRATION ICS PLATFORM IOxOS IFC1420 (??) BEAM DIAGNOSTIC PLATFORM STRUCK SIS8300KU + SIS8900

BCM AMC migration Based on STRUCK MTCA.4 HW we will migrate the actual BCM design to the new AMC based on XILINX Kintex Ultrascale (KU): First migration: should be on the Struck native FPGA framework that is mostly similar to the Virtex6 (L2) framework (same proprietary interfaces, part of the design is not based on HDL file but netlist): according to BPM experience we expect the same performance ADC; All the mathematical core will need a wrapper because on the new technology are AXI based; Next step: working with LLRF we are developing a new framework based on AXI bus, so it will be necessary to rebuilt most of the HDL that was interfacing to the Struck proprietary framework, but it will make the design more maintainable and solve some issue related to the Struck native framework (missing arbiter betweene DDR – PCIe –ADC)

BCM AMC migration (2) ICS platform is based instead on the IOxOS IFC 1420 AMC (FMC carrier) that mount the same XILINX Kintex Ultrascale of the Struck SIS8300KU AMC: This is a complete different framework, but it has in the TOSCA III crossbar an AXI interface to their proprietary protocol, so if we have already migrated the FW design to KU it will be much more easy to migrate to the ICS platform; There will be many difference on the memory management, shared memory area, access to the ADC, etc…. But there will be the ICS/PSI support to migrate the working design to the TOSCA III; Still there are no samples to make any test because the design phase it is still on PCB review!!!

ESS BCM FIRMWARE ESS platform migration BCM Optical Link ESS DEVENV for IKCs

BCM L2 optical Link The bidirectional optical link is needed to provide the current measurement, or the raw data, to the next BCM that is (for logistic reason) implemented on an AMC that sit in a crate in a different rack; To the LLRF cavity controller to use the information to improve the quality of the beam.

BCM based on Struck Struck SIS8300 has 2 SFP cage available on the front panel: Xilinx provide an easy to use fast serial protocol (AURORA) based on a proprietary frame/streaming interface, that include the GTX/GTH configuration using Core Generator: this mean that only a FIFO based interface to the actual design need to be designed; Each ADC samples at 88 MSps, each sample is 16 bit, that means 1.5 Gbps, the aurora protocol has an overahed of 3% so: The L2 AMC mount a Virtex6 FPGA that has GTX transceiver up to 6.5 Gbps: so only 4/8 channel could transported on the link The KU AMC mount a Kintex Utrascale that has GTH transceiver up to 16 Gbps so all the 10 channels.

ESS BCM FIRMWARE ESS platform migration BPM Optical Link ESS DEVENV for IKCs

ICS Continuous Integration/Delivery Courtesy of ICS JAVA flow

FPGA design/delivery Logs and documentation Notification Bitstream Development Environment Repository 12

branch branch branch branch minor feature major feature Feature branch Master branch V1.0.0 V1.1.0 V1.1.1 V2.0.0 Production branch hotfix branch http://semver.org/ MAJOR.MINOR.PATCH MAJOR version when you make incompatible API changes MINOR version when you add functionality in a backwards-compatible manner PATCH version when you make backwards-compatible bug fixes

Notification Manual acceptance Production Branch commit Simulate Logs (Simulation, Synthesis, Mapping, Routing) Documentation Simulation results Manual acceptance Scripts Patterns Golden Model Configuration Constrains AMC Folder structure Bitstream V1.0.0 Production Branch commit Simulate FPGA Flow Notification

Frameworks on bitbucket STRUCK project contains different repository for FW and SW for the SIS8300L/L2/KU, each of it has 2 branch for the 2 RTM used: for BCM (SIS8900 RTM); for BPM (DWC8300 downconverter RTM); IOxOS project contains the TOSCA III firmware for IFC1410 that support streaming of data from a ADC 3110/3111 - FMC Mezzanine Card

Questions 16

17