L-Shaped RST Routing Perform L-RST using node b as the root

Slides:



Advertisements
Similar presentations
Triangle partition problem Jian Li Sep,2005.  Proposed by Redstar in Algorithm board in Fudan BBS.  Motivated by some network design strategy.
Advertisements

OCV-Aware Top-Level Clock Tree Optimization
O(N 1.5 ) divide-and-conquer technique for Minimum Spanning Tree problem Step 1: Divide the graph into  N sub-graph by clustering. Step 2: Solve each.
Discrete Structures Lecture 13: Trees Ji Yanyan United International College Thanks to Professor Michael Hvidsten.
Minimum Spanning Trees
5/14/ Routing Prof. Shiyan Hu Office: EERC 731.
Fuzzy Simulated Evolution for Power and Performance of VLSI Placement Sadiq M. Sait Habib Youssef Junaid A. KhanAimane El-Maleh Department of Computer.
Probability-based approach for solving the Rectilinear Steiner tree problem Jayakrishnan Iyer.
Efficient Merging and Construction of Evolutionary Trees Andrzej Lingas,Hans Olsson, and Anna Ostlin Journal of Algorithms 2001 Reporter: Jian-Fu Dong.
Chapter 5 Trees PROPERTIES OF TREES 3 4.
Insert A tree starts with the dummy node D D 200 D 7 Insert D
> >
Minimal Spanning Trees. Spanning Tree Assume you have an undirected graph G = (V,E) Spanning tree of graph G is tree T = (V,E T E, R) –Tree has same set.
Chapter 4: Trees AVL Trees Lydia Sinapova, Simpson College Mark Allen Weiss: Data Structures and Algorithm Analysis in Java.
Circuit Simulation Based Obstacle-Aware Steiner Routing Yiyu Shi, Paul Mesa, Hao Yu and Lei He EE Department, UCLA Partially supported by NSF Career Award.
6/29/ Routing Prof. Shiyan Hu Office: EERC 731.
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
MST: Red Rule, Blue Rule. 2 MST Instance
Floorplanning. Obtained by subdividing a given rectangle into smaller rectangles. Each smaller rectangle corresponds to a module.
Bed Separation Single and Bunk Beds –A minimum of 6 feet separation must be maintained between beds when heads of beds are oriented in the same direction.
TOP – DOWN Splay Trees Bottom-up splaying requires traversal from root to the node that is to be splayed, and then rotating back to the root – in other.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 FLUTE: Fast Lookup Table Based RSMT Algorithm.
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
Block-level 3D IC Design with Through-Silicon-Via Planning Dae Hyun Kim, Rasit Onur Topaloglu, and Sung Kyu Lim Department of Electrical and Computer Engineering,
Minimum Spanning Tree Given a weighted graph G = (V, E), generate a spanning tree T = (V, E’) such that the sum of the weights of all the edges is minimum.
Fundamentals of Algorithms MCS - 2 Lecture # 7
COSC 2007 Data Structures II Chapter 14 Graphs III.
Minimum Routing Cost Spanning Trees Kun-Mao Chao ( 趙坤茂 ) Department of Computer Science and Information Engineering National Taiwan University, Taiwan.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
GLARE: Global and Local Wiring Aware Routability Evaluation Yaoguang Wei1, Cliff Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi Reddy,
Deferred Decision Making Enabled Fixed- Outline Floorplanner Jackey Z. Yan and Chris Chu DAC 2008.
Design of Novel Two-Level Quantizer with Extended Huffman Coding for Laplacian Source Lazar Velimirović, Miomir Stanković, Zoran Perić, Jelena Nikolić,
MCA 202: Discrete Structures Instructor Neelima Gupta
ERT/SERT Algorithm (1/16)Practical Problems in VLSI Physical Design Elmore Routing Tree (ERT) Algorithm Perform ERT algorithm under 65nm technology  Unit-length.
1-Steiner Algorithm (1/17)Practical Problems in VLSI Physical Design 1-Steiner Routing by Kahng/Robins Perform 1-Steiner Routing by Kahng/Robins  Need.
Prof. Shiyan Hu Office: EERC 518
Routing Topology Algorithms Mustafa Ozdal 1. Introduction How to connect nets with multiple terminals? Net topologies needed before point-to-point routing.
STEINER TREE BASED ALGORITHMS. INTRODUCTION Maze routing and line probing algorithms cannot be used for multiterminal nets. There are several approaches.
Reading a vernier caliper
Polygon Fill Flood fill algorithm. The algorithm starts at a pixel and perform a depth first traversal of the adjacent pixels and fills the visited pixel.
VLSI Quadratic Placement
Section 8.1 Trees.
Parallel Graph Algorithms
Multi-Commodity Flow Based Routing
Models for the Layout Problem
FlowMap Algorithm Perform clustering on the following 2-bounded network Intra-cluster and node delay = 0, inter-cluster = 1 Pin constraint = 3 Practical.
Sequence Pair Representation
Visualizing Prim’s MST Algorithm Used to Trace the Algorithm in Class
Connected Components Minimum Spanning Tree
Tree Construction (BFS, DFS, MST) Chapter 5
Minimum Spanning Tree.
Iterative Deletion Routing Algorithm
GORDIAN Placement Perform GORDIAN placement
A-tree Routing Algorithm
Abstract Data Structures
Bounded Radius Routing
Bed Separation Single and Bunk Beds
Binary Tree Traversals
GRAPH AND FIGURES OF SOMS : Rigid BODIES
Spanning Tree Algorithms

Successive Shortest Path Algorithm
Steiner Min/Max Tree Routing
Zero Skew Clock tree Implementation
Parallel Graph Algorithms
Prim’s Minimum Spanning Tree Algorithm Neil Tang 4/1/2008
Clock Tree Routing With Obstacles
Red Black Trees Top-Down Deletion.
Lecture 8 Huffman Encoding (Section 2.2)
FLUTE: Fast Lookup Table Based RSMT Algorithm for VLSI Design
Presentation transcript:

L-Shaped RST Routing Perform L-RST using node b as the root First step: build a separable MST Prim with w(i,j) = (D(i,j), −|y(i) − y(j)|, − max{x(i), x(j)}) Practical Problems in VLSI Physical Design

First Iteration Practical Problems in VLSI Physical Design

Separable MST Construction Practical Problems in VLSI Physical Design

Separable MST Construction (cont) Practical Problems in VLSI Physical Design

Constructing a Rooted Tree Node b is the root node Based on the separable MST (initial wirelength = 32) Bottom-up traversal is performed on this tree during L-RST routing Practical Problems in VLSI Physical Design

Partial L-RST for Node C Practical Problems in VLSI Physical Design

Partial L-RST for Node E Practical Problems in VLSI Physical Design

Partial L-RST for Node G Practical Problems in VLSI Physical Design

Partial L-RST for Node D Practical Problems in VLSI Physical Design

Partial L-RST for Node D (cont) Practical Problems in VLSI Physical Design

Partial L-RST for Node F best case Practical Problems in VLSI Physical Design

Partial L-RST for Node F (cont) best case Practical Problems in VLSI Physical Design

Processing the Root Node best case Practical Problems in VLSI Physical Design

Top-down Traversal In order to obtain the final tree upper upper lower Practical Problems in VLSI Physical Design

Final Tree Wirelength reduction Initial wirelength − total overlap = 32 − 4 = 28 Practical Problems in VLSI Physical Design

Stable Under Rerouting Steiner points are marked X Wirelength does not reduce after rerouting Practical Problems in VLSI Physical Design