Overview: - Front-end activities - DAQ activities - Test beam analysis Bologna activities Mauro Villa INFN & Università di Bologna Overview: - Front-end activities - DAQ activities - Test beam analysis 1

Strip readout architecture under development BOLOGNA pixel-like hit extraction architecture Pre-trigger buffer array PISA Sparsifiers FE Ctrl logic Buf #k ... #1 4 bit ToT readout/slow control strip #127 strip #0 ~hit_rate * trig_latency BUF #1 Triggered hits only How many buffers? How many barrels? Asynchronous logic assumed: Triggered event size not known a-priori (thus readout time as well) F. Giorgi

Strip readout chip simulations Strip FE architecture defined, modeled and simulated. Digital readout efficiency measured value (simulations) ~100% with buffer depth = 32 2 MHz/strip : Layer 0 buffer size 16 32 64 buffered hits 3.8 M 12.9 M of which triggered 23363 76850 output triggered hits 14679 76849 triggered hit lost 8684 1 Efficiency (%) 62.8 99.9987 100 Buffer Depth Scan 760 kHz/strip : Layer 1 buffer size 8 16 32 buffered hits 1.4 M 7 M of which triggered 8748 28829 output triggered hits 6788 28825 triggered hit lost 1960 4 Efficiency (%) 77.6 99.986 100 F. Giorgi

Digital periferical logic blocks Progs, Triggers, clocks: Embedded in the readout architecture and actually part of it. It allows the trigger latency control, clock handling, channel masking, running Serializer Interface: Sends out data (16 bits wide) on a programmable number of lines (1, 2, 4, 6) Protocol (8b/10b?) and implementation to be defined. Analog and buffers Barrels and readout ✔ Progs, Triggers clocks Serializer

Clock, Trigger, Registers Now Future Current set-up is flexible  7 I/O lines 6 inputs: Reset, Clock (60MHz), FastClock (180 MHz?),Timestamp, Trigger, RegIn 1 Output: RegOut NB: SuperB trigger protocol not yet defined Contr: no redundancy Minimal number of lines: 2 inputs: FastClock (180 MHz?), RegIn 1 output: RegOut Requires assumptions on trigger protocol Clock, Timestamp and triggers have to be in sync on the whole system!

SVT data load updates Chip features Triggered, 128 channels, 60 MHz clock, 60/120/180 MHz output clock, serialized output. 2 Data word: Time-stamp-like and hit Hit: 7 bits Channel ID, 4 bits ToT, 1 bit word type, 4 bits to be defined, for a total of 16 bits Timestamp: 10 bits Timestamp, 1 bit word type, 5 bits to be defined, for a total of 16 bits Updated background simulation from R. Cenci (apr 2012) Renormalization for pairs, rad bhabha and geometry -18%, -15% on average rates for inner layers Inclusion of beam gas  +35% in outer layers

172 GROS, 172 1-Gbps links, 18 FEBoards, <88 kB/event Layer layer Type Chip/ROS Avai chans back. rate MHz/ cm2 (safety = 5) Hits in BCO Occupancy in BCO Grouping Triggered Gbit/s/GROS FE Boards Event Size (hits) Striplet u 6 768 151 33 4.3% 1 0.99 2 5277 Striplet v Strip z 7 896 14 18.5 2.0% 0.56 2223 Strip phi 16 21.2 2.4% 0.64 2540 9.6 18.0 0.54 2163 10.3 19.3 2.2% 0.58 2321 3 10 1280 4.2 16.8 1.31% 0.50 2017 3.0 12.1 1.58% 0.36 1455 4a 5 640 0.28 1.3 0.20% 0.26 1357 4 512 0.43 1.9 0.38% 0.38 2048 4b 0.21% 1406 2.0 0.39% 0.40 2121 5a 0.15 0.9 0.13% 0.17 1012 0.22 1.2 0.24% 0.24 1458 5b 0.14% 1043 0.25% 0.25 1502 172 GROS, 172 1-Gbps links, 18 FEBoards, <88 kB/event

Maximum data lines per chip Lines/ROS at 180 MHz 12 7 14 10 6 5 4   Max HIT strip rate (kHz) DAQ Time window (us) Hits/ chip per Trig. Words per chip per trigger Bits per chip per trig. bandwidth (Mbit/s) Lines at 60 MHz Lines at 120 MHz Lines at 180 MHz Chip/ROS L0 U 1910 0.3 73.3 83.3 1667 250 6 3 2 V L1 Z 810 31.1 41.1 822 123 1 7 PHI 1740 66.8 76.8 1536 230 5 L2 865 33.2 43.2 864 130 1220 46.8 56.8 1137 170 4 L3 770 29.6 39.6 791 120 10 980 37.6 47.6 952 140 L4 29.4 39.4 789 235 30.1 47.1 802 L5 15.4 25.4 507 76 150 19.2 29.2 584 88 1,2,4 lines per chip usable at 120 MHz on all SVT 14 lines per module max at 180 MHz (16 bits serializers)

DAQ Activities ongoing Optical 1 Gbit/s Example of a read-out section Front-end chips Optical Link 2.5 Gbit/s to ROM UPILEX+Cu (?) FEB C Copper bus Serdes or FPGA Detector fibers HDIs ~1-2 m LV1 Transition card Studies ongoing for fixed-latency data transmission over optical fibers. Latencies have to be measurable for: Clock, Timestamp and Trigger Test beds for optical links and latencies measurements in place: using xilinx FPGA SerDes Front-End board: component selection phase

Further DAQ activities Preparation for November Beam-Test: Update of software infrastructure (ATLAS TDAQ-04-00-01) Minor updates on firmware except for the on-board RAM buffer loss of 50% of events DAQ rate in 2011 BT (kHz) 40% of recon-structed single track events

BEAM-TEST STRIPLETS DATA ANALYSIS Laura FABBRI & Lorenzo VITALE Reporting work done in Bologna & Trieste : Striplets as DUT (layer 0 detector) Efficiency measurements Cluster multiplicities Spatial resolutions

BEAM TEST SETUP (2011) SPS@CERN telescope 120 GeV π+/- DUT

STRIPLET CHANNELS OCCUPANCY run 2276 S1 inactive channels: Side U: 0, 1, 2, 6,134, 229, 381, 382, 383 Side V: 0, 1, 2, 36, 38, 64, 108,131,132, 133, 134, 135, 136,137, 138, 139, 140, 182, 324, 381, 382, 383 13

INACTIVE CHANNELS EXCLUSION run 2277 Inactive strips and their closest channels are excluded by selection in efficiency computation Telescope accept. striplets space point (cm) inactive region (cm) Events with more than one track are rejected Events with tracks hitting inactive or hot strips and their closest channels are excluded from efficiency calculation.

EFFICIENCIES: SIDE U AND SIDE V Efficiency: percentage of events in the DUT active region within 112μm/cos to the reconstructed track ( = angle of incidence) ( 7 RMS). Results from different runs are consistent within 0.1%. Both for low and high threshold an efficiency better than 99% is measured.  εU Low thr. ε U High thr. ε V 99.6 99.4 15 99.7 99.5 30 45 99.8 60 99.2 70 99.9

Efficiencies (%) within 80/cosϑ vs incident angle ( 5 RMS) Incident angle Eff_U Low thr. High thr. Eff_V 99.5 99.4 99.3 15 30 99.6 45 99.7 60 99.8 70 Going from 7 RMS to 5 RMS gives a -0.1 % change June 1, 2012 L. Vitale

Comparisons Low/High thr.: 0˚ - Cluster size/Residuals June 1, 2012 L. Vitale

Comparisons Low/High thr.: 45˚ - Cluster size/Residuals June 1, 2012 L. Vitale

Comparisons Low/High thr.: 70˚ - Cluster size/Residuals June 1, 2012 L. Vitale

Summary on cluster size Multiplicity increases with the angle of incidence  Close to expectations at low thresholds No significant increase of noise.

Resolutions from RMS Residual Incident angle Reso_U Low thr. RMS (mm) High thr. Reso_V 16.4 15.9 15.2 16.6 15 12.8 13.9 13.6 15.5 30 14.4 14.2 14.5 15.8 45 18.3 17.6 21.0 22.8 60 24.3 28.6 36.0 41.1 70 36.8 52.3 56.3 62.0 June 1, 2012 L. Vitale

Resolution from Residuals RMS is solid, but too rough estimate for the resolution. To improve several fits were tried. The best results were given by 5 Gauss + Const: Core Gauss 3 free parameters (Ntot, Mean, Sigma) 2 Gauss +-25mm 1 free parameter (same Mean, Sigma as Core) 2 Gauss +-50mm 1 free parameter (same Mean, Sigma as Core) June 1, 2012 L. Vitale 22

Resolutions Residual vs incident angle Sigma CORE (Frac CORE) Resi_U Low thr. s(mm) Frac% Reso_U High thr. Reso_V 12.0 99.5 12.8 99.7 13.4 99.9 15 8.6 97.9 10.6 99.4 10.9 12.4 99.6 30 10.2 97.2 9.4 96.6 10.3 94.8 11.0 95.1 45 13.7 97.0 93.4 16.8 94.2 16.4 77.0 60 16.5 90.9 17.3 67.8 21.0 50.4 20.3 30.8 70 23.8 83.1 32.6 42.0 34.9 30.2 37.0 June 1, 2012 L. Vitale

Analysis work in progress Still to be done Cross check resolutions In progress: Cross check Pulse Height Resolutions for different cluster size Paper writing

BO activity: future steps Next monthes will be devoted to: Closure of some FE chip details number of input/output lines Look for a configurable data serializer Finalization of a FEB board prototype (or parts of it) Preparation of the next beam tests Need software, firmware and hardware updates Need to start as soon as possible Striplet analysis finalization

first layer of telescope BEAM SPOT AND DIVERGENCES run 2277 (cm) (cm) first layer of telescope 27

MISALIGNMENT OF TELESCOPE wrt BEAM AXIS trigger: 1-8-8 => beam hit at least 4 layer x 5 4 3 2 1 excluded by trigger top view beam dark area the dark area is in the positive x region for the first three layers and in the negative region for the latter. (cm) (cm) 28

RESIDUAL AFTER ALIGNMENT Alignment and DUT Residuals: select events with only one track passing from DUT active area, compute residuals for DUT space points, perform iterative alignment minimizing residuals vs U,V translations and rotations.

3D–IC submissions - Layout Readout circuits placed and routed Post layout circuit (clock-trees, pads) simulated (some problems with std-cell timing library) Static Timing analysis converging (Encounter) PADS disposition almost defined. Definitive routing when all custom blocks are closed. APSEL_VI 5034 um x 9800 um die area 70 k Std-Cell readout Readout power estimate min 100 mW (1.08 V, +125C) slow max 200 mW (1.65, -40C) fast SuperPix1 matrix 2 rows of staggered pads 146 um pitch 130 um pitch  3255 um x 9421 um die area 40k Std-Cell readout Readout power estimate min 70 mW (1.08 V, +125C)  slow max 140 mW (1.65, -40C) fast

ANGULAR SCAN run angle 2278 0° 2279 15° 2280 30° 2281 45° 2282-2283 Six positions between 0° and 70° thresholds = 20 (high), 15 (low) run angle 2278 0° 2279 15° 2280 30° 2281 45° 2282-2283 60° 2284-2285 70°

ANGULAR SCAN: CLUSTER MULTIPLICITY SIDE U

ANGULAR SCAN: CLUSTER MULTIPLICITY SIDE V 34

CLUSTER MULTIPLICITY: HIGH vs LOW TH.

DAQ reading chain for L0-L5 DAQ chain independent on the chosen FE options Optical 1 Gbit/s Example of a read-out section Front-end chips Optical Link 2.5 Gbit/s to ROM UPILEX+Cu (?) FEB C Copper bus Serdes or FPGA ROM Detector fibers HDIs ~1-2 m LV1 Transition card High rad area 15Mrad/year Off detector low rad area Counting room Std electronics Data Encoder IC .... Specs are under discussion Rad-hard serializer to be finalized  looking into a low power/low speed version Copper tail: lenght vs data transfer to be studied 36

Comparisons Low/High thr.: 0˚ - Cluster size/Residuals June 1, 2012 L. Vitale 37

Comparisons Low/High thr.: 15˚ - Cluster size/Residuals June 1, 2012 L. Vitale 38

Comparisons Low/High thr.: 30˚ - Cluster size/Residuals June 1, 2012 L. Vitale 39

Comparisons Low/High thr.: 45˚ - Cluster size/Residuals June 1, 2012 L. Vitale 40

Comparisons Low/High thr.: 60˚ - Cluster size/Residuals June 1, 2012 L. Vitale 41

Comparisons Low/High thr.: 70˚ - Cluster size/Residuals June 1, 2012 L. Vitale 42

Cluster size vs incident angle Cluster size U Low thr. High thr. Cluster size V Cluster size V Expected by geom. 1.3 1.2 1+ 15 1.5 1.4 30 2.0 1.8 1.9 1.7 1.6+ 45 2.9 2.6 2.7 2.3 2.8 60 4.6 3.9 4.0 3.0 4.9 70 6.9 5.2 5.3 3.3 7.8 June 1, 2012 L. Vitale

Cluster size vs incident angle Cluster size U Low thr. High thr. Cluster size V Cluster size V Expected by geom. 1.3 1.2 1+ 15 1.5 1.4 30 2.0 1.8 1.9 1.7 1.6+ 45 2.9 2.6 2.7 2.3 2.8 60 4.6 3.9 4.0 3.0 4.9 70 6.9 5.2 5.3 3.3 7.8 June 1, 2012 L. Vitale 44

15˚ - 5Gauss Fit of Residuals June 1, 2012 L. Vitale 45

30˚ - 5Gauss Fit of Residuals June 1, 2012 L. Vitale 46

45˚ - 5Gauss Fit of Residuals June 1, 2012 L. Vitale 47

60˚ - 5Gauss Fit of Residuals June 1, 2012 L. Vitale 48

70˚ - 5Gauss Fit of Residuals June 1, 2012 L. Vitale 49

FEB Board functionalities FE chip clock, timestamp and trigger signals distribution Check and keep FE chips (>1600) in sync ! Configure FE chips (MB of data to upload), provide calibration mechanisms Convert SuperB LVL1 signal to SVT trigger signal (timestamp aware) Acquire FE hits, provide a first data compression TS stripping, hit packing (clusterization?) Send data to ROM HW monitoring of data 50

ETD knowns and unknowns Known: ECS (Experiment Control System) protocol is ethernet Known: ROM link is optical. Guaranteed 1 Gbps, aiming at larger bandwidths (2.5, 5 or more Gbps). Unknown: rad-hard serializer and optical link to be put on detector (assuming fixed latency, 1 Gbps). Unknown: Hosting crates (VMEx, ACTA) 51

SuperB-FEB Board schematics Gb ethernet Large FPGA DAQ link 2.5 Gbit/s VME! VME FPGA Or uCPU L1/Spare DAQ link 4x1 Gbit/s FE links FCTS interface Small FPGA 4x1 Gbit/s FE links ECS interface Memory Small FPGA Planning For changes And extensions 4x1 Gbit/s FE links Small FPGA FCTS protocol to be decided experiment-wide Large FPGA for data shipping and monitoring VME FPGA or uCPU might be included in the large FPGA. 52

Input mezzanines Input optical links on mezzanines to easy future upgrades 4 1-Gbps optical link mezzanine compatible with EDRO available for tests Small FPGA (spartan) and memory on board 53

Hit and Trigger generation and read out Bare Assumptions: Readout clock: 60 MHz Time stamp clock: 30 MHz Trigger rate: 150 kHz Fully triggered SVT DAQ Acquisition window: 300 ns (L0-L3), 1 us (L4-L5) Latency <10 us Buffers in chip and in reading chain wide enough for eff>99.8% Optical link 1 Gbit/s ; 2.5 Gbit/s to ROM Background rates from latest BRUNO simulations with safety factors 5 54

R. Cenci, dec 2011; factor >2 increase SVT Background rates Background simulation: Strip detail implemented in Bruno for a more accurate rate calculation R. Cenci, dec 2011; factor >2 increase Data volumes and bandwidths SVT data volumes and bandwidths are mostly independent on the details of the design, but are defined mainly by background, trigger rates and DAQ time windows. 55

SVT Data rates, links and boards MC data from R. Cenci, dec 2011 Layer Modules HDI ReadOut Section (ROS) Grouped ROS FEBoard Plain rate Data to ROM/ FEBoard (Gbps) 0 (pixel) 8 16 32 4 5.7 1 6 12 24 2 6.9 6.3 3 5.9 64 1.7 5 18 36 72 1.2 Total/mean 60 120 240 172  3.5 (strip) Needs: 172 1-Gbps links, 18 Front-End Boards Average event size: 60 kB. 2.5 Gbps links NOT usable. Needed a factor 2-3 data compression. 56

Il pairing riduce le hits Layer 1 Layer 3 Il pairing riduce le hits e quindi i rates

Be aware of Safety Factors around Trigger rate: 150 kHz SF: 1.5 Hit width (14 vs 12) SF: 1.2 DAQ Acquisition window SF: 1.5 Optical link 1 Gbit/s SF: 1.2 Background rates SF: 5 Ignored clusterization (pixels) SF: 1.2-1.5 (?) Pairing and Gangling (strips) SF: 1-1.5 (?) 58

SVT Data rates, links and boards Layer Modules HDI ReadOut Section (ROS) Grouped ROS FEBoard Plain rate Data to ROM/ FEBoard (Gbps) 0 (pixel) 8 16 32 12 1.9 1 6 24 2.3 2 2.1 3 4 64 1.7 5 18 36 72 1.2 Total/mean 60 120 240 172  38 1.9 (strip) Needs: 172 1-Gbps links, 38 Front-End Boards & 38 ROMs Average event size: 60 kB. 2.5 Gbps links usable. 59

DAQ Summary Data chain outlined; FEB functionalities clear Major (ETD common) unknowns: 1 Gbps optical link types (bidirectional?) Serdes/FPGA Crate type SVT data volumes and bandwidths are mostly independent on the details of the design. MC (Bkg) simulation still not 100% reliable. Safety factors all around. Probably still too large. 100% uncertainty on the number of FEB board! No showstopper seen in the “upper” part: FEB & ROMs. 60 60

TDR – SVT readout electronics Readout chain schema and reference to the relevant SVT parts (FE and hybrids) (Transition card) Serializers / Links / Trigger / HV) Design of the Readout Card Input data links/Data compression/Output links Fast (Trigger) and slow (configuration) signals handling Final Data rates and data volumes 61