ESE535: Electronic Design Automation

Slides:



Advertisements
Similar presentations
Architecture-dependent optimizations Functional units, delay slots and dependency analysis.
Advertisements

SCORE - Stream Computations Organized for Reconfigurable Execution Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, Yury Markovskiy Andre DeHon, John.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 21: April 15, 2009 Routing 1.
Penn ESE Fall DeHon 1 ESE (ESE534): Computer Organization Day 19: March 26, 2007 Retime 1: Transformations.
Dataflow Process Networks Lee & Parks Synchronous Dataflow Lee & Messerschmitt Abhijit Davare Nathan Kitchen.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 12: March 2, 2009 Sequential Optimization (FSM Encoding)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 8: February 11, 2009 Dataflow.
CS294-6 Reconfigurable Computing Day 23 November 10, 1998 Stream Processing.
Penn ESE Spring DeHon 1 ESE (ESE534): Computer Organization Day 5: January 24, 2007 ALUs, Virtualization…
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 8: February 13, 2008 Retiming.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 24: April 18, 2011 Covering and Retiming.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 10: February 18, 2015 Architecture Synthesis (Provisioning, Allocation)
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 7: February 3, 2002 Retiming.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 20: April 8, 2015 Sequential Optimization (FSM Encoding)
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 15: March 13, 2013 High Level Synthesis II Dataflow Graph Sharing.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 25: April 17, 2013 Covering and Retiming.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 5: January 31, 2011 Scheduling Variants and Approaches.
CS137: Electronic Design Automation
ESE532: System-on-a-Chip Architecture
Invitation to Computer Science, C++ Version, Fourth Edition
ESE534: Computer Organization
ESE532: System-on-a-Chip Architecture
Overview Parallel Processing Pipelining
ESE532: System-on-a-Chip Architecture
ESE532: System-on-a-Chip Architecture
ESE532: System-on-a-Chip Architecture
Multiscalar Processors
2. Specification and Modeling
ESE534 Computer Organization
CS137: Electronic Design Automation
ESE532: System-on-a-Chip Architecture
ESE532: System-on-a-Chip Architecture
ESE532: System-on-a-Chip Architecture
Lecture 25 More Synchronized Data and Producer/Consumer Relationship
ESE532: System-on-a-Chip Architecture
ESE532: System-on-a-Chip Architecture
Invitation to Computer Science, Java Version, Third Edition
Processor (I).
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
Introduction to cosynthesis Rabi Mahapatra CSCE617
ESE535: Electronic Design Automation
Day 26: November 1, 2013 Synchronous Circuits
Lesson 4 Synchronous Design Architectures: Data Path and High-level Synthesis (part two) Sept EE37E Adv. Digital Electronics.
ESE535: Electronic Design Automation
ECE-C662 Introduction to Behavioral Synthesis Knapp Text Ch
ESE535: Electronic Design Automation
ESE535: Electronic Design Automation
HIGH LEVEL SYNTHESIS.
ESE535: Electronic Design Automation
Computer Architecture
ESE535: Electronic Design Automation
Jinquan Dai, Long Li, Bo Huang Intel China Software Center
Guest Lecture by David Johnston
CS184a: Computer Architecture (Structures and Organization)
ESE535: Electronic Design Automation
ESE534: Computer Organization
ESE535: Electronic Design Automation
Superscalar and VLIW Architectures
ESE535: Electronic Design Automation
ESE534: Computer Organization
ARM ORGANISATION.
ESE535: Electronic Design Automation
COMPUTER ORGANIZATION AND ARCHITECTURE
ESE532: System-on-a-Chip Architecture
ESE532: System-on-a-Chip Architecture
ESE532: System-on-a-Chip Architecture
Prof. Onur Mutlu Carnegie Mellon University
Multiprocessors and Multi-computers
Presentation transcript:

ESE535: Electronic Design Automation Day 13: March 2, 2011 Dataflow Penn ESE535 Spring 2011 -- DeHon

Previously Scheduling of concurrent operations A7 A8 B11 A9 B2 B3 B4 Penn ESE535 Spring 2011 -- DeHon

Want to see Abstract compute model natural for parallelism and hardware Describe computation abstracted from implementation Defines correctness Penn ESE535 Spring 2011 -- DeHon

Today Dataflow SDF Dynamic Dataflow Expression Single rate Multirate Behavioral (C, MATLAB, …) RTL Gate Netlist Layout Masks Arch. Select Schedule FSM assign Two-level, Multilevel opt. Covering Retiming Placement Routing Today Dataflow SDF Single rate Multirate Dynamic Dataflow Expression Penn ESE535 Spring 2011 -- DeHon

Parallelism Motivation Penn ESE535 Spring 2011 -- DeHon

Producer-Consumer Parallelism Stock predictions encrypt Can run concurrently Just let consumer know when producer sending data Penn ESE535 Spring 2011 -- DeHon

Pipeline Parallelism Can potentially all run in parallel ME DCT VQ code Can potentially all run in parallel Like physical pipeline Useful to think about stream of data between operators Penn ESE535 Spring 2011 -- DeHon

Plishker Router Task Example Penn ESE535 Spring 2011 -- DeHon

DAG Parallelism Doesn’t need to be linear pipeline Synchronize inputs Decode video Check/decode block synchronize Decode audio Doesn’t need to be linear pipeline Synchronize inputs Penn ESE535 Spring 2011 -- DeHon

Graphs with Feedback + In general may hold state Very natural for many tasks Penn ESE535 Spring 2011 -- DeHon

Definitions Penn ESE535 Spring 2011 -- DeHon

Dataflow / Control Flow Control flow (e.g. C) Program is a sequence of operations Operator reads inputs and writes outputs into common store One operator runs at a time defines successor Dataflow Program is a graph of operators Operator consumes tokens and produces tokens All operators run concurrently Penn ESE535 Spring 2011 -- DeHon

Token Data value with presence indication May be conceptual Only exist in high-level model Not kept around at runtime Or may be physically represented One bit represents presence/absence of data Penn ESE535 Spring 2011 -- DeHon

Token Examples? What are familiar cases where data may come with presence tokens? Network packets Memory references from processor Variable latency depending on cache presence Penn ESE535 Spring 2011 -- DeHon

Operator Takes in one or more inputs Computes on the inputs Produces a result Logically self-timed “Fires” only when input set present Signals availability of output Penn ESE535 Spring 2011 -- DeHon

Penn ESE535 Spring 2011 -- DeHon

Dataflow Graph Represents Abstractly computation sub-blocks linkage controlled by data presence Penn ESE535 Spring 2011 -- DeHon

Dataflow Graph Example Penn ESE535 Spring 2011 -- DeHon

In-Class Dataflow Example Penn ESE535 Spring 2011 -- DeHon

Stream Logical abstraction of a persistent point-to-point communication link Has a (single) source and sink Carries data presence / flow control Provides in-order (FIFO) delivery of data from source to sink stream Penn ESE535 Spring 2011 -- DeHon

Streams Captures communications structure Abstract communications Explicit producerconsumer link up Abstract communications Physical resources or implementation Delay from source to sink Penn ESE535 Spring 2011 -- DeHon

Dataflow Abstracts Timing Doesn’t say on which cycle calculation occurs [contrast RTL] Does say What order operations occur in How data interacts i.e. which inputs get mixed together Permits Scheduling on different # of resources Operators with variable delay [examples?] Variable delay in interconnect [examples?] Penn ESE535 Spring 2011 -- DeHon

Examples Operators with Variable Delay Variable delay interconnect Cached memory or computation Shift-and-add multiply Iterative divide or square-root Variable delay interconnect Shared bus Distance changes Wireless, longer/shorter cables Computation placed on different cores? Penn ESE535 Spring 2011 -- DeHon

Difference: Dataflow Graph/Pipeline Penn ESE535 Spring 2011 -- DeHon

Clock Independent Semantics Interconnect Takes n-clocks Penn ESE535 Spring 2011 -- DeHon

Semantics Need to implement semantics i.e. get same result as if computed as indicated But can implement any way we want That preserves the semantics Exploit freedom of implementation Penn ESE535 Spring 2011 -- DeHon

Dataflow Variants Penn ESE535 Spring 2011 -- DeHon

Synchronous Dataflow (SDF) Particular, restricted form of dataflow Each operator Consumes a fixed number of input tokens Produces a fixed number of output tokens When full set of inputs are available Can produce output Can fire any (all) operators with inputs available at any point in time Penn ESE535 Spring 2011 -- DeHon

Synchronous Dataflow + ×k Penn ESE535 Spring 2011 -- DeHon

SDF: Execution Semantics while (true) Pick up any operator If operator has full set of inputs Compute operator Produce outputs Send outputs to consumers Penn ESE535 Spring 2011 -- DeHon

Multirate Synchronous Dataflow Rates can be different Allow lower frequency operations Communicates rates to CAD Something not clear in RTL Use in scheduling, provisioning Rates must be constant Data independent decimate 2 1 Penn ESE535 Spring 2011 -- DeHon

SDF Can validate flows to check legal Like KCL  token flow must be conserved No node should be starved of tokens Collect tokens Schedule onto processing elements Provisioning of operators Provide real-time guarantees Simulink is SDF model Penn ESE535 Spring 2011 -- DeHon

SDF: good/bad graphs 1 2 1 Penn ESE535 Spring 2011 -- DeHon

SDF: good/bad graphs 1 2 1 2 Penn ESE535 Spring 2011 -- DeHon

Dynamic Rates? When might static rates be limiting? Compress/decompress Lossless Even Run-Length-Encoding Filtering Discard all packets from geraldo Anything data dependent Penn ESE535 Spring 2011 -- DeHon

Data Dependence Add Two Operators Switch Select Penn ESE535 Spring 2011 -- DeHon

Switch Penn ESE535 Spring 2011 -- DeHon

Filtering Example Geraldo? discard dup switch Penn ESE535 Spring 2011 -- DeHon

Select Penn ESE535 Spring 2011 -- DeHon

Constructing If-Then-Else Penn ESE535 Spring 2011 -- DeHon

Select Example select select In-Order Merge of Streams (smallest to largest) > switch switch select Penn ESE535 Spring 2011 -- DeHon

Looping for (i=0;i<Limit;i++) Penn ESE535 Spring 2011 -- DeHon

Dynamic Challenges In general, cannot say If a graph is well formed Will not deadlock How many tokens may have to buffer in stream Right proportion of operators for computation Penn ESE535 Spring 2011 -- DeHon

Expression Penn ESE535 Spring 2011 -- DeHon

Expression Could express operators in C/Java Each is own thread Link together with Streams E.g. SystemC Penn ESE535 Spring 2011 -- DeHon

C Example while (!(eos(stream_a) && !(eos(stream_b)) A=stream_a.read(); B=stream_b.read(); Out=(a+b)*(a-b); stream_out.write(Out); Penn ESE535 Spring 2011 -- DeHon

Connecting up Dataflow stream stream1=new stream(); operator prod=new stock(stream1); operator cons=new encrypt(stream1); Stock predictions encrypt Penn ESE535 Spring 2011 -- DeHon

Summary Dataflow Models Allow Simple pipelines DAGs SDF (single, multi)-rate Dynamic Dataflow Allow express parallelism freedom of implementation Penn ESE535 Spring 2011 -- DeHon

Admin Homework 4 Due Today Spring Break next week Back on Monday 3/14 Reading on Blackboard Penn ESE535 Spring 2011 -- DeHon

Big Ideas: Dataflow Abstract representations Natural model for capturing computations Communicates useful information for optimization Linkage, operator usage rates Abstract representations Leave freedom to implementation Penn ESE535 Spring 2011 -- DeHon