Recovery: Redirect fetch unit to T path if actually T.

Slides:



Advertisements
Similar presentations
Dynamic Branch PredictionCS510 Computer ArchitecturesLecture Lecture 10 Dynamic Branch Prediction, Superscalar, VLIW, and Software Pipelining.
Advertisements

Dynamic Branch Prediction
Pipeline Hazards Pipeline hazards These are situations that inhibit that the next instruction can be processed in the next stage of the pipeline. This.
EECE476: Computer Architecture Lecture 21: Faster Branches Branch Prediction with Branch-Target Buffers (not in textbook) The University of British ColumbiaEECE.
The Light at the End of the Tunnel – Doesn’t Mean You Died ! Part 3 - Branch Hazards – Easier! – 3/24/04 This is a control hazard – as opposed to data.
Computer Architecture 2011 – Branch Prediction 1 Computer Architecture Advanced Branch Prediction Lihu Rappoport and Adi Yoaz.
EECS 470 Branch Prediction Lecture 6 Coverage: Chapter 3.
1 COMP 206: Computer Architecture and Implementation Montek Singh Wed., Oct. 8, 2003 Topic: Instruction-Level Parallelism (Dynamic Branch Prediction)
1 COMP 206: Computer Architecture and Implementation Montek Singh Mon., Oct. 7, 2002 Topic: Instruction-Level Parallelism (Dynamic Branch Prediction)
EENG449b/Savvides Lec /17/04 February 17, 2004 Prof. Andreas Savvides Spring EENG 449bG/CPSC 439bG.
Goal: Reduce the Penalty of Control Hazards
Trace Caches J. Nelson Amaral. Difficulties to Instruction Fetching Where to fetch the next instruction from? – Use branch prediction Sometimes there.
Branch Target Buffers BPB: Tag + Prediction
COMP381 by M. Hamdi 1 Pipelining Control Hazards and Deeper pipelines.
Computer Architecture Instruction Level Parallelism Dr. Esam Al-Qaralleh.
COMP381 by M. Hamdi 1 (Recap) Control Hazards. COMP381 by M. Hamdi 2 Control (Branch) Hazard A: beqz r2, label B: label: P: Problem: The outcome.
1 COMP 740: Computer Architecture and Implementation Montek Singh Thu, Feb 19, 2009 Topic: Instruction-Level Parallelism III (Dynamic Branch Prediction)
Dynamic Branch Prediction
EENG449b/Savvides Lec /25/05 March 24, 2005 Prof. Andreas Savvides Spring g449b EENG 449bG/CPSC 439bG.
Prophet/Critic Hybrid Branch Prediction Falcon, Stark, Ramirez, Lai, Valero Presenter: Christian Wanamaker.
Pipelined Datapath and Control (Lecture #15) ECE 445 – Computer Organization The slides included herein were taken from the materials accompanying Computer.
Evaluation of Dynamic Branch Prediction Schemes in a MIPS Pipeline Debajit Bhattacharya Ali JavadiAbhari ELE 475 Final Project 9 th May, 2012.
Computer Architecture: A Constructive Approach Branch Direction Prediction – Six Stage Pipeline Joel Emer Computer Science & Artificial Intelligence Lab.
Ch2. Instruction-Level Parallelism & Its Exploitation 2. Dynamic Scheduling ECE562/468 Advanced Computer Architecture Prof. Honggang Wang ECE Department.
1 Dynamic Branch Prediction. 2 Why do we want to predict branches? MIPS based pipeline – 1 instruction issued per cycle, branch hazard of 1 cycle. –Delayed.
Branch.1 10/14 Branch Prediction Static, Dynamic Branch prediction techniques.
Korea UniversityG. Lee CRE652 Processor Architecture Dynamic Branch Prediction.
CSC 4250 Computer Architectures October 31, 2006 Chapter 3.Instruction-Level Parallelism & Its Dynamic Exploitation.
Computer Architecture: A Constructive Approach Next Address Prediction – Six Stage Pipeline Joel Emer Computer Science & Artificial Intelligence Lab. Massachusetts.
Computer Structure Advanced Branch Prediction
Computer Architecture 2015 – Advanced Branch Prediction 1 Computer Architecture Advanced Branch Prediction By Yoav Etsion and Dan Tsafrir Presentation.
CS 6290 Branch Prediction. Control Dependencies Branches are very frequent –Approx. 20% of all instructions Can not wait until we know where it goes –Long.
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB ECE232: Hardware Organization and Design Part 13: Branch prediction (Chapter 4/6)
Computer Architecture 2015– Pipeline 1 Computer Architecture Pipeline By Yoav Etsion & Dan Tsafrir Presentation based on slides by David Patterson, Avi.
CSL718 : Pipelined Processors
Real-World Pipelines Idea Divide process into independent stages
Instruction-Level Parallelism and Its Dynamic Exploitation
CS203 – Advanced Computer Architecture
Computer Structure Advanced Branch Prediction
Dynamic Branch Prediction
Computer Architecture Advanced Branch Prediction
CS5100 Advanced Computer Architecture Advanced Branch Prediction
COSC3330 Computer Architecture Lecture 15. Branch Prediction
Ammar: Branch & Pipelines.
PowerPC 604 Superscalar Microprocessor
CSE 431 Computer Architecture Fall 2005 Lecture 12: SS Front End (Fetch , Decode & Dispatch) Mary Jane Irwin ( )
Samira Khan University of Virginia Nov 13, 2017
Chapter 4 The Processor Part 4
Samira Khan University of Virginia Dec 4, 2017
CMSC 611: Advanced Computer Architecture
TIME C1 C2 C3 C4 C5 C6 C7 C8 C9 I1 branch decode exec mem wb bubble
Constructive Computer Architecture Tutorial 5 Epoch & Branch Predictor
Pipelined Processor Design
Branch statistics Branches occur every 4-6 instructions (16-25%) in integer programs; somewhat less frequently in scientific ones Unconditional branches.
Systems I Pipelining II
Dynamic Branch Prediction
Branch Prediction: Direction Predictors
Control unit extension for data hazards
Lecture 10: Branch Prediction and Instruction Delivery
Advanced Microarchitecture
Branch Prediction: Direction Predictors
Pipelining: dynamic branch prediction Prof. Eric Rotenberg
Control unit extension for data hazards
Dynamic Hardware Prediction
Wackiness Algorithm A: Algorithm B:
Control unit extension for data hazards
Tutorial 7: SMIPS Labs and Epochs Constructive Computer Architecture
Computer Structure Advanced Branch Prediction
Spring 2019 Prof. Eric Rotenberg
Spring 2019 Prof. Eric Rotenberg
Presentation transcript:

Recovery: Redirect fetch unit to T path if actually T. IF stage ID stage 2 PC 4 + 1 NPC + taken target Imm Actual T/NT A op 0 ? taken? decode is a branch Always predict NT. 1 Recovery: Redirect fetch unit to T path if actually T. 2

IF stage ID stage == 4 PC BTB NPC + taken target Imm target read port A op 0 ? decode taken target Actual T/NT is a branch write port read port IF stage ID stage hit t/nt target T/NT pred. == Predicted T/NT mispredicted?

BTB miss OR (BTB hit & prev. outcome = NT) + PC BTB NPC 4 Imm A op 0 ? decode taken target Actual T/NT is a branch write port read port IF stage ID stage hit t/nt target T/NT pred. == Predicted T/NT mispredicted? 1 Predict NT if: BTB miss OR (BTB hit & prev. outcome = NT) 1

(BTB hit & prev. outcome = T) + PC BTB NPC 4 Imm A op 0 ? decode taken target Actual T/NT is a branch write port read port IF stage ID stage hit t/nt target T/NT pred. == Predicted T/NT mispredicted? 2 Predict T if: (BTB hit & prev. outcome = T) 2

Recovery: Redirect fetch unit to NT path if: + PC BTB NPC 4 Imm A op 0 ? decode taken target Actual T/NT is a branch write port read port IF stage ID stage hit t/nt target T/NT pred. == Predicted T/NT mispredicted? 3 Recovery: Redirect fetch unit to NT path if: (Predicted T & Actually NT) 3

Recovery: Redirect fetch unit to T path if: + PC BTB NPC 4 Imm A op 0 ? decode taken target Actual T/NT is a branch write port read port IF stage ID stage hit t/nt target T/NT pred. == Predicted T/NT mispredicted? 4 Recovery: Redirect fetch unit to T path if: (Predicted NT & Actually T) 4

IF stage ID stage == Update BTB: 4 PC BTB NPC + taken target Imm A op 0 ? decode taken target Actual T/NT is a branch write port read port IF stage ID stage hit t/nt target T/NT pred. == Predicted T/NT mispredicted? 5 Update BTB: If branch missed in BTB, add it to BTB. Whether branch missed or hit in BTB, always update prev. outcome field. 5

Backup Slides

Training BTB IF stage ID stage Taken Target T / NT direction PC 4 + NPC + Taken Target Imm read port BTB A op 0 ? T / NT direction decode is a branch write port PC

Using BTB IF stage ID stage Taken Target == is a branch 4 PC BTB PC + NPC + Taken Target Imm target read port BTB t/nt A op 0 ? Actual T/NT hit T/NT pred. Predicted T/NT == mispredicted? write port decode is a branch PC