PNOISE Analysis of Pipelined ADCs Josh Carnes OSU

Sampled Signal Analysis Over-sampling Under-sampling * = * =

Sampled Signal Analysis Any spectrum energy outside of the Nyquist range gets folded/aliased into baseband Full spectrum of noise is folded into the baseband BW limited noise Noise Folding due to ideal sampling +1 -1 -1 +1 +2 -2 -2 +2 +3 -3 -3 +3

PNOISE Analysis The SpectreRF PNOISE simulates the amount of noise in a frequency range for a periodic system, including “folded” noise from modulated bands Determines total circuit noise or individual contributions as a total integrated noise or PSD Simulation parameters determine accuracy/speed tradeoff Requires a preceding PSS analysis

PSS Analysis for PNOISE Calculates the periodic operating point Only single clock is applied, additional stimulus disabled Relevant PSS parameters Beat Frequency – clock frequency Output harmonics – … not important maxacfreq – Accuracy parameter

PSS Analysis Forms

PNoise Analysis for Pipelined ADCs Want to pick a specific time during period to calculate noise (sampling instant) Want PSD calculated for impulse sampling Do Not Want dependence on (sinc) Noise Shaping effect of S/H Time Domain PNOISE Analysis

PNoise Analysis for Pipelined ADCs 2 important mode parameters to consider and set Noise Type (PNoise) = Time Domain Reference sideband (PNoise) = 0 3 important accuracy parameters to consider and set maxsideband (PNoise) = sweep range (PNoise) = (100 Hz, 100 MHz) maxacfreq (PSS/options) =

Accuracy Parameters maxacfreq, maxsideband will define PNOISE accuracy Consider noise folded in from nth harmonic: maxsideband = n Some noise missed, maxacfreq too low for desired maxsideband

Accuracy Parameters Derived for single pole BW limited white noise [4] Applicable to sampling switch kT/C noise Identify “significant” sampling network with largest BW fp = pole frequency [Hz] fs = sampling frequency [Hz] %err = allowed rms noise error of noise source [%]

PNOISE Analysis Form

The Sampling Instant TD PNOISE wants to calculate PSD at sampling instant Difficult to sync TD with exact sampling moment … or you can do something easier … “save” voltage at sampling instant with an ideal S/H Can enter any time value during hold operation

The Sampling Instant

Tstab and S/H Sampling Tstab PSS parameter Allows for initial conditions to settle TD Noise sampling of ideal S/H AVOID CLOCK EDGES! Run PSS first Note clock edge times In PNOISE(TD), set Number of Points = 0 Set Add Specific Point to some point between clock edges NOTE: all times are relative to PSS time interval

TD PNoise: Pipelined ADC Rvref Rf MDAC model Some resistor noise contributes to kT/C of stage Other resistor noise sampled by next stage caps Opamp noise modeled with equivalent input thermal resistance Feedback factor = ½ ugbw = 240 MHz Expected noise: Φ2 Rs C Φ1 Rn Φ1p C Φ1 Φ1p Φ1 Φ1p Φ1 D Φ2 Rvref = 200 Rf = 200 Rs = 600 Rn = 100 C = 1p

TD PNoise: Pipelined ADC Time-domain PNoise simulation

TD PNoise: Pipelined ADC Noise summary (input referred) V2 Noise Type: Time-domain Sim1: N=16 fstop= 50MHz maxacfreq= 1.65GHz Sim2: N=20 fstop= 50MHz maxacfreq= 2.05GHz Noise voltage error Stage Noise Source Expected Sim1 Sim2 Error (sim1,sim2) 1 kT/C 4.14n 3.6n 3.76n 6.7%, 4.7% 2 1.04n 0.91n 0.93n 6.5%, 5.7% 3 0.26n 0.23n 0.235n 5.9%, 5% Rf 0.31n 0.32n 1.6%, 1.6% 0.078n 0.081n 2%, 2% Rvref 0.078 OpAmp 0.625n 0.646n 1.7%, 1.7% 0.156n 0.163n 2.2%, 2.2% TOTAL 7n 6.35n 6.54n 4.8%, 3.3%

Words of Caution Flicker Noise: how do I set low end of sweep range? Linear or log sweep? Linear sweep can severely overestimate noise due to insufficient points in flicker noise region Accuracy: This can’t be right!!! Open your mind to noise mechanisms you haven’t considered (particularly correlation) or noise estimations made along the way Try a sim with very tight accuracy settings Work your way up from an ideal model

Words of Caution Verilog Hidden State Additional sources of noise in Pipelined ADCs With no input signal, reference noise will not be excited

References [1] C.A. Gobet, “Spectral Distribution of a Sampled 1st-Order Lowpass Filtered White Noise,” Electronics Letters, vol. 17, pp. 720-721, Sep. 1981. [2] C.A. Gobet, A. Knob, “Noise Analysis of Switched Capacitor Networks,” IEEE Trans. Circuits and Systems, vol. cas-30, pp. 37-43, Jan. 1983. [3] J.H. Fischer, “Noise Sources and Calculation Techniques for Switched Capacitor Filters,” IEEE J. Solid-State Circuits, vol. sc-17, pp. 742-752, Aug. 1982. [4] K. Kundert, “Simulating Switched-Capacitor Filters with SpectreRF,” The Designer’s Guide Community, www. http://www.designers-guide.org/, 2005. [5] K. Kundert, “An Introduction to Cyclostationary Noise,” The Designer’s Guide Community, www. http://www.designers-guide.org/, 2005. [6] K. Kundert, “Device Noise Simulation of Delta-Sigma Modulators,” The Designer’s Guide Community, www. http://www.designers-guide.org/, 2005. [7] SpectreRF manual – found in Cadence tools help menu