Circuit Timing Dr. Tassadaq Hussain www.tassadaq.ucerd.com

Digital Timing: Clock Signals, Waveforms Dr. Tassadaq Hussain Riphah International University Microsoft Barcelona Supercomputing Center 2

Clock Signal When sending digital signals, a 0 or 1 is being sent. However, for different devices to communicate, timing information needs to be associated with the bits sent. Digital waveforms are referenced to clock signals. You can think of a clock signal as a conductor that provides timing signals to all parts of a digital system so that each process may be triggered at a precise moment. A clock signal is a square wave with a fixed period. The period is measured from the edge of one clock to the next similar edge of the clock; most often is it measured from one rising edge to the next. The frequency of the clock can be calculated by the inverse of the clock period 3 3

Critical Path A critical path is the sequence of project network activities which add up to the longest overall duration, regardless if that longest duration has float or not.

Jitter Jitter is the deviation from the ideal timing of an event to the actual timing of an event.

Drift Clock drift occurs when the transmitter’s clock period is slightly different from that of the receiver.

Rise Time, Fall Time, and Aberrations Even with drift, in theory, when a digital signal goes from a 0 to a 1, it would happen instantaneously. However, in reality, it takes time for a signal to change between high and low levels. Rise time (trise) is the time it takes a signal to rise from 20 percent to 80 percent of the voltage between the low level and high level. Fall time (tfall) is the time it takes a signal to fall from 80 percent to 20 percent of the voltage between the low level and high level.

Overshoot, preshoot, and undershoot are collectively called aberrations

Settling Time After a digital signal has reached a voltage level, it bounces a little and then settles to a more constant voltage. The settling time (ts) is the time required for an amplifier, relay, or other circuit to reach a stable mode of operation. In the context of digital signal acquisition, the settling time for full-scale step is the amount of time required for a signal to reach a certain accuracy and stay within that range.

Hysteresis Hysteresis refers to the difference in voltage levels between the detection of a transition from logic low to logic high, and the transition from logic high to logic low. It can be calculated by subtracting the input high voltage from the input low voltage.

Skew Skew is when the clock signal arrives at different components at different times. Unlike drift, the clock signals have the same period; they just arrive at different times. This can be caused by a variety of factors including wire length, temperature variation, or differences in input capacitance. Channel-to-channel skew generally refers to the skew across all data channels on a device. When each sample is acquired, the point in time at which each data channel is sampled with respect to every other data channel is not identical, but the difference is within some small window of time called the channel-to-channel skew.

Eye Diagram Rise time in the diagram is the mean of the individual rise times. The slope indicates sensitivity to timing error; the smaller the better. Fall time in the diagram is the mean of the individual fall times. The slope indicates sensitivity to timing error; the smaller the better. The width of the logic high value is the amount of distortion in the signal (set by the signal-to-noise ratio). The signal-to-noise ratio at the sampling point is from the eye width to the bottom or the logic high-voltage range. Jitter of the signal. The most open part of the eye is when there is the best signal-to-noise ratio and is thus the best time to sample.

OR gate Example

Timing Concepts and Terminology Combinational Timing Constraints: Gate Propagation Delay Critical Path Delay Flip-Flop Timing Constraints Clock-to-Q Delay Setup Time Hold Time Circuit Speed Minimum Clock Period Maximum Clock Frequency

Gate Delay (Propagation Delay) Time that it takes for combinational gate output to change after inputs change A B Y B Y t gate A

Path Delay A X B C D Y Delay through a series of combinational gates. Specifically, the time it takes for the output of the series of gates to change after the inputs to the path change. Example: Propagation delay for each gate is the same (1ns in this example) B C D X Y A

Path Delay Delay through a series of combinational gates. Specifically, the time it takes for the output of the series of gates to change after the inputs to the path change. Example: Propagation delay for each gate is the same (1ns in this example) B C D X Y A 0 1 2 3 4 5

Comments on the Previous Cct In the previous circuit, if we apply all inputs at time 0, then after 5ns, all the outputs have settled to their final values. Note: 1. Some outputs might settle earlier 2. Some outputs may switch back and forth a few times before settling to a final value Do you see any problem with this?

How to Synchronize Inputs? Rising edge on clock at time 0. Assuming no delay in the flip-flops, the outputs of the source (left four) flip-flops change at time 0. Some time later (one clock cycle), the clock goes high again, and the destination flip-flops read in X and Y Add flip-flops! X Y D Q D Q other circuitry A B C D

In General Digital systems are made up of many stages of flip-flops and combinational logic. DFF DFF DFF … Combinational Logic Combinational Logic

You’ve Seen this Before Finite State Machines, shift registers, counters, etc… Output Logic DFF Next State Logic FSM Inputs Outputs D Q 1 clock reset load Parallel Inputs Parallel Outputs

How fast can we run the clock?

Clock’s purpose is to tell flip-flops when to read in data How fast can we run the clock? Clock’s purpose is to tell flip-flops when to read in data Combinational Logic DFF …

How fast can we run the clock? On clock edge, new inputs sent into combinational logic Key Idea Combinational Logic DFF …

How fast can we run the clock? On clock edge, new inputs sent into combinational logic Takes some time for outputs to settle Key Idea Combinational Logic DFF …

How fast can we run the clock? On clock edge, new inputs sent into combinational logic Takes some time for outputs to settle Don’t want to read in new outputs before they are ready Key Idea Combinational Logic DFF …

Critical Path Delay Critical Path: Critical Path Delay: The path (source FF output to destination FF input) with the longest delay Critical Path Delay: The delay of the critical path

Critical Path Delay: Example D Q D Q other circuitry A B C D Critical Path: B  AND  INV  OR  OR  AND  X Critical Path Delay: 5ns Clock period cannot be smaller than 5ns or else X register will read in wrong data

Max Clock Frequency / Min Clock Period Critical path delay limits the clock period (and hence clock frequency) tClockMin  tCritcalPath From the example tCritcalPath  5ns  tClockMin  5ns 1  f   200MHz ClockMax 5ns

What happens if you run the clock SLOWER? No problem! Combinational logic has more than enough time to settle fClock  fClockMax tClock  tCriticalPath 

What happens if you run the clock FASTER? WRONG DATA READ INTO OUTPUT FLIP-FLOPS Combinational logic does NOT have enough time to settle to correct value Note: This only applies to your critical path(s). Your non-critical path FFs might still be ok, but you need to design for the worst-case. fClock  fClockMax tClock  tCriticalPath 

Critical Path in Entire Design Since a single clock controls all flip-flops in all stages, you need to look for the critical path amongst all stages DFF DFF DFF Combinational Combinational … Logic tcrit0 Logic tcrit1 max foreach pathi tcrit _ i  tCriticalPath 

Critical Path in Entire Design: Example Y D Q clk

Flip-Flop Timing Constraints

t clk-to-q Clock-to-Q Delay D D C LK Q CLK Q The time that it takes for the output of a Flip-Flop to settle after the clock rising-edge occurs D DFF D C LK Q CLK Q t clk-to-q Note: the delay may not be exactly the same for the cases when Q changes from 1 to 0 or 0 to 1. Therefore, clk-to-q delay is often given as a max and a min value.

Setup Time t setup D C LK Q Input to flip-flop cannot change for a certain amount of time PRIOR to clock rising-edge. D DFF D C LK Q CLK t setup Time for input to propagate “into” the flip-flop before clock arrives

t hold Hold Time D Q C LK CLK Input to flip-flop cannot change for a certain amount of time AFTER clock rising-edge. DFF D C LK Q CLK t hold Time for flip-flop to fully read input before the value is “taken away”

Summary of Flip-Flop Timing t setup t hold Don’t change value on D during this time! D DFF D C LK Q CLK Q t clk-to-q

How fast can we run the clock? Revisited to account for flip-flop constraints

Two Requirements Setup Requirement Hold Requirement Input values must be ready for destination flop ahead of when the rising clock edge arrives. Also known as MaxPath Timing Constraint. Hold Requirement Input values of destination flop must not change for a short time after rising clock edge. Also known as MinPath Timing Constraint.

tClock  tclktoq max  tCriticalPath  tsetup Setup Requirement tClock  tclktoq max  tCriticalPath  tsetup After clock rising-edge, there must be enough time so that source flip-flop’s output can settle to correct value critical path can settle to correct value value arrives at destination flip-flop early enough for setup time DFF DFF Combinational Logic

before FF reads in value Key Concept for Setup Time: Must have enough time for input of FF to settle before FF reads in value

Hold Requirement Remember, after rising edge of clock, FF is now reading in data. Input to the FF cannot change for thold amount of time! Unlikely to be a problem for Critical Path Need to be careful for the fast (non-critical) path Key: Consider what happens when the same clock edge is considered at both the source and destination flops.

tclktoq min  tpath  thold Hold Requirement In general, for all paths: tclktoq min  tpath  thold Minimum clk-to-q delay because we need to design for the fastest possible arrival time of signal to destination flop Note: On each clock cycle, flip-flop is BOTH reading in a new value (when you look at it as a destination flip-flop) AND providing a value to the next stage (when you look at it as a source flip-flop)

Hold Requirement Violation Example DFF Critical Path tCriticalPath fast path tFastPath Say that we violate Hold Requirement: tclktoq min  tFastPath  thold After clock rising-edge, source flip-flop’s output settles fast path settles SUPER QUICKLY to correct value destination flop is still reading in “old” value from fast path logic (i.e. hold time has not yet passed for that reading) (i.e The new value from source FF can get there so fast that when the clock arrives the new value may change before it has been latched into destination FF.)

GOOD NEWS! CAD Tools handle all this for you! How to Fix Timing Violations? Setup Violation: Slow down clock Move registers around (reduce length of critical path) Hold Violation: CANNOT address by changing clock frequency! Can add more gate-delays to path (e.g. add buffers) GOOD NEWS! CAD Tools handle all this for you! But its not an excuse! the material in this slide set will definitely be on the exam

Example: Timing Analysis Given flip-flop timing parameters: tsu = 0.6 ns, th = 0.4 ns, and 0.8 ns ≤ tcQ ≤ 1.0 ns Not delay: 1.1ns Find out Fmax and hold time violations?

Example: Timing Analysis Tmin = 1/Fmax Consider all paths in the circuit that start and end at flip-flops Tmin = tcQ + tNOT + tsu Tmin = 1.0 + 1.1 + 0.6 = 2.7 ns Fmax = 1/2.7 ns = 370.37 MHz

Example: Timing Analysis Hold time violation: examine the shortest possible delay from a positive clock edge to a change in the value of the D input. The delay is given by tcQ + tNOT = 0.8 + 1.1 = 1.9 ns. Since 1.9 ns > th = 0.4 ns there is no hold time violation.

Class Exercise: Timing Analysis Assume the same FF timing parameters as we did in our previous example. Assume the gate delay of 1.2ns. Calculate the maximum clock frequency for which this circuit will operate properly and find out if there is any hold-time Violation?

Class Exercise: Timing Analysis There are many paths in this circuit that start and end at flip-flops. The longest such path starts at flip-flop Q0 and ends at flip-flop Q3. Aka: Critical Path The delay of the critical path includes the clock-to-Q delay of flip-flop Q0, the propagation delay through three AND gates, and one XOR-gate delay. Tmin = tcQ + 3(tAND) + tXOR + tsu Tmin = 1.0 + 3(1.2) + 1.2 + 0.6 ns = 6.4 ns Fmax = 1/6.4 ns = 156.25 MHz The shortest paths through the circuit are from each flip-flop to itself, through an XOR gate. The minimum delay along each such path is tcQ + tXOR = 0.8 + 1.2 = 2.0 ns. Since 2.0 ns > th = 0.4 ns there are no hold time violations.

Glitches

Glitch An undesired short-lived pulse that occurs before a signal settles to its intended value Causes: Unequal arrival times of inputs on combinational gates Various electrical effects (not covered in this course)

Glitch Example C A B D 1) A, B settle after clock-to-q delay DFF C XOR A B D B C D 1 2a) B arrives immediately at XOR, causing a transition to 1 on D after one gate delay 2b) At the same time, A arrives at the INV immediately, causing a transition to 1 on C after one gate delay 3) After C settles, its value arrives at the XOR after one additional gate delay, causing a transition back to 0 on D CLK A B C D t clk-to-q t gate Glitch 1) A, B settle after clock-to-q delay

Glitches – Key Takeaways A signal may switch several times before settling to final intended value. This is OK if … it settles before anyone tries to do something with that data. i.e. Before a flip-flop tries to read it on the rising edge of next clock cycle Power and Energy Considerations: Designers care about glitches because they consume unnecessary power! Any transition consumes power because the circuit is doing work to move electrons around.

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on Circuit Performance Clock Skew and it’s impact on Circuit Performance

Clock Skew When the same sourced clock signal arrives at different components at different times!

Clock Skew - Causes When the same sourced clock signal arrives at different components at different times! Causes: Various electrical effects, (not covered in this course): wire-interconnect length temperature variations capacitive coupling material imperfections and differences in input capacitance on the clock inputs

Skew Types Positive Skew: Negative Skew: Zero Skew: Occurs when the transmitting register receives the clock tick earlier than the receiving register. Negative Skew: Occurs when the receiving register gets the clock tick earlier than the sending register. Zero Skew: Refers to the arrival of the clock tick simultaneously at transmitting and receiving register.

Impact of Skew on Circuit Performance Assuming that the clock signal still arrives at flip-flops Q0, Q1, and Q2 simultaneously, but that there is a delay in the arrival of the clock signal at flip-flop Q3. Previously the critical path through the circuit was from flip-flop Q0 to Q3. The clock skew at Q3 has the effect of reducing this delay, because it provides additional time before data is loaded into this flip-flop. Taking a clock skew of 1.5 ns into account, the delay of the path from flip-flop Q0 to Q3 is given by: tcQ + 3(tAND) + tXOR + tsu − tskew = 6.4 − 1.5 ns = 4.9 ns

Impact of Skew on Circuit Performance There is now a different critical path through the circuit, which starts at flip-flop Q0 and ends at Q2. The delay of this path gives Tmin = tcQ + 2(tAND) + tXOR + tsu = 1.0 + 2(1.2) + 1.2 + 0.6 ns = 5.2 ns Fmax = 1/5.2 ns = 192.31 MHz In this case the clock skew results in an increase in the circuit’s maximum clock frequency. But if the clock skew had been negative, which would be the case if the clock signal arrived earlier at flip-flop Q3 than at other flip-flops, then the result would have been a reduced Fmax.

Impact of Skew on Circuit Performance Since the loading of data into flip-flop Q3 is delayed by the clock skew, it has the effect of increasing the hold time requirement of this flip-flop to th + tskew, for all paths that end at Q3 but start at Q0, Q1, or Q2. The shortest such path in the circuit is from flip-flop Q2 to Q3 and has the delay tcQ + tAND + tXOR = 0.8 + 1.2 + 1.2 = 3.2 ns. Since 3.2 ns > th + tskew = 1.9 ns there is no hold time violation.

Clock Skew

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What does the CAD Tool do with the Timing?

Based on register-register delays Page 68

Quartus II can show you the worst-case timing paths: Page 69

Task for Evaluation + Previous Tasks Design a Sequential and Combinatinal (Seq/Comb) Circuit Use ISE Design Compiler for Synthesis RTL Code Calculate the Critical Path of above Seq/Comb Logic using ISE Calculate the throughput and latency of seq/comb circuit using modelsim. Reduce latency and improve throughput of seq/comb circuit by applying piplining techniques