ECE 352 Digital System Fundamentals Flip-Flop Timing Parameters In this presentation, we will look at flip-flop timing issues.

Flip-Flop Timing Parameters A flip-flop only behaves the way we expect it to if we make sure that its synchronous inputs do not change too close to the clock edge If a synchronous input changes too close to the clock edge, the correct value may not be stored! The output of a flip-flop will not update instantaneously at the active clock – there will be a delay before Q is known to be correct As much as possible, we try to deal with idealized behavior, and ignore the complexities of low-level details. When designing circuits with flip-flops, we generally want to think about their functional behavior, which assumes that the values on its inputs immediately before the active clock edge affect its stored value and thus its output immediately after the clock edge. But, unfortunately, the “immediately” part is not exactly true. In fact, we need to ensure that synchronous signals are at the correct value some time before the clock edge, and we need to make sure they stay at that value for some time after the clock edge, or the flip-flop may not operate correctly. Also, the flip-flop can’t update immediately because it takes time for the new value to propagate through the flip-flop to the Q output.

Flip-Flop Timing Parameters We need to ensure that our clock frequency is not too fast for the design of our circuit A newly-stored value must propagate through its FF and any combinational logic on the way to the next FF, and arrive “early” enough before the next clock edge We need to know: When do values need to get to the FF? How long do they need to stay after the edge? How long for them to propagate through the FF? How long is the path between flip-flops? based on flip-flop design & technology All of these issues are related to ensuring that our circuit actually works the same way as it does in a functional simulation. In particular, we need to make sure that we do not try to make our circuit go faster than it actually can. So we need to verify that the circuit will operate correctly with the intended clock frequency. To do this, we need to consider the flip-flop timing parameters as well as the delays due to the combinational logic in the circuit. We’ll talk about flip-flop timing parameters in this video, and discuss sequential circuit timing issues in the next video. based on the design of the logic circuit

Flip-Flop Setup Time (ts) Synchronous flip-flop inputs must be stable for a certain time before each active clock edge clock period ts The flip-flop’s synchronous inputs must not change for a specified time before the active clock edge. This interval is called the set-up time, or tS for short. tS is the time that the input must be “set-up” before it can be correctly stored. If the input changes during this interval, the flip-flop may store the wrong value. The actual value of the set-up time is a function of the transistor technology, the operating voltage, and how the flip-flop was constructed, so the manufacturer will specify it. Input must not change

Flip-Flop Hold Time (th) Synchronous flip-flop inputs must be stable for a certain time after each active clock edge clock period th The synchronous inputs must also remain stable for a short time AFTER the active clock edge. This interval is called the hold time, or tH for short. tH is the time you must hold the input constant to ensure it is stored correctly. If the input is allowed to change during the hold time, the flip-flop may store the incorrect value. The value of tH is also specified by the manufacturer. Input must not change

Flip-Flop Propagation Delay (tpd) The flip-flop output will not reflect the new stored value until some time after the active clock edge clock period tpd The flip-flop Q output will not update instantaneously after the clock edge. Instead, the manufacturer will specify the maximum time it may take for the output to update. This delay is the flip-flop propagation delay, or tPD for short. The output will be correct somewhere within this interval, but we don’t know exactly when. So, we have to assume the worst, which means that we assume that the Q output isn’t valid until the end of the tPD interval. Output not yet updated

Flip-Flop Timing Parameters clock period ts th ts th Here we show all three timing parameters relative to the active clock edge. The set-up and hold time form an interval around the active clock edge in which the synchronous inputs cannot change. The propagation delay represents a time interval during which the value of the flip-flop output is not guaranteed to be correct. Input must not change tpd tpd Output not yet updated

Flip-Flop Timing Parameters Setup (ts) and hold (th) times: Changes to FF input during these times may or may not be reflected in the stored value… DO NOT change the FF input values during these times This also means you should not have the circuit inputs change on active clock edges when simulating a circuit! Propagation delay (tpd) Takes some time after the clock edge for the stored FF value to “show up” at outputs Clock period Clock can only go so fast and still have the FFs behave in an expected manner due to the above Let’s review the flip-flop timing parameters. In practice, the actual values of these parameters would be supplied by the flip-flop manufacturer. In this class, we will always provide the values for you. You don’t need to remember any specific values, but you DO need to know the meaning and significance of each of the parameters. If we violate the set-up and hold time restrictions, the flip-flop may not store the correct value. We need to ensure by our circuit design that the synchronous flip-flop inputs will not change during these intervals. This idea also applies in simulation – you should never change a circuit input at the active clock edge, or the simulator won’t know which comes first – the change on the clock or the change on the synchronous input. We need to account for the length of time it takes a value to propagate through the flip-flop when calculating how fast we can clock a sequential circuit. In fact, the upper limit to the achievable clock frequency for a given sequential circuit is determined in part by these flip-flop timing parameters.

ECE 352 Digital System Fundamentals Flip-Flop Timing Parameters In the next video, we’ll look at how we use the flip-flop timing parameters, as well as combinational logic delays, to calculate how fast we can clock our sequential circuits and still have them operate correctly.