74LS283 4-Bit Binary Adder with Fast Carry

Slides:



Advertisements
Similar presentations
L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.
Advertisements

1 ECE 4436ECE 5367 Computer Arithmetic I-II. 2 ECE 4436ECE 5367 Addition concepts 1 bit adder –2 inputs for the operands. –Third input – carry in from.
Chapter 4 -- Modular Combinational Logic. Decoders.
Comparator.
Fast Adders See: P&H Chapter 3.1-3, C Goals: serial to parallel conversion time vs. space tradeoffs design choices.
Binary Addition. Binary Addition (1) Binary Addition (2)
CSE-221 Digital Logic Design (DLD)
ECE C03 Lecture 61 Lecture 6 Arithmetic Logic Circuits Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
Lecture 8 Arithmetic Logic Circuits
Chapter 5 Arithmetic Logic Functions. Page 2 This Chapter..  We will be looking at multi-valued arithmetic and logic functions  Bitwise AND, OR, EXOR,
Digital Arithmetic and Arithmetic Circuits
WEEK #10 FUNCTIONS OF COMBINATIONAL LOGIC (ADDERS)
Chapter # 5: Arithmetic Circuits
Chapter 6-1 ALU, Adder and Subtractor
5-1 Programmable and Steering Logic Chapter # 5: Arithmetic Circuits.
Carry look ahead adder P (I) = a(I) xor b(I); G(I) = a(I) and b(I); S(I) = p(I) xor c(I); Carry(I+1) = c(I)p(I) + g(I)
درس مدارهای منطقی دانشگاه قم مدارهای منطقی محاسباتی تهیه شده توسط حسین امیرخانی مبتنی بر اسلایدهای درس مدارهای منطقی دانشگاه.
COE 202: Digital Logic Design Combinational Circuits Part 2 KFUPM Courtesy of Dr. Ahmad Almulhem.
1 Lecture 12 Time/space trade offs Adders. 2 Time vs. speed: Linear chain 8-input OR function with 2-input gates Gates: 7 Max delay: 7.
1 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here.
Lecture #23: Arithmetic Circuits-1 Arithmetic Circuits (Part I) Randy H. Katz University of California, Berkeley Fall 2005.
Carry-Lookahead & Carry-Select Adders
Lecture 12 Logistics Last lecture Today HW4 due today Timing diagrams
Lecture Adders Half adder.
Addition and multiplication
Space vs. Speed: Binary Adders
Lecture 12 Modular Design Topics Adder and Subtractor Design
Summary Half-Adder Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out.
XOR, XNOR, and Binary Adders
Combinational Circuits
ECE 331 – Digital System Design
CSE Winter 2001 – Arithmetic Unit - 1
Topic 3b Computer Arithmetic: ALU Design
Lecture 14 Logistics Last lecture Today
King Fahd University of Petroleum and Minerals
Arithmetic Functions & Circuits
XOR, XNOR, & Binary Adders
Arithmetic Circuits (Part I) Randy H
Sabyasachi Das Synplicity Inc Sunil P. Khatri Texas A&M University
Instructor: Alexander Stoytchev
Instructor: Alexander Stoytchev
Number Systems and Circuits for Addition
Unit 5 COMBINATIONAL CIRCUITS-1
Topic 3b Computer Arithmetic: ALU Design
Digital Systems Section 12 Binary Adders. Digital Systems Section 12 Binary Adders.
CS 140 Lecture 14 Standard Combinational Modules
Logic Gates.
Overview Part 1 – Design Procedure Part 2 – Combinational Logic
Part III The Arithmetic/Logic Unit
CSE 140 Lecture 14 Standard Combinational Modules
Instructor: Alexander Stoytchev
Addition and multiplication
Instructor: Mozafar Bag-Mohammadi University of Ilam
Lecture 14 Logistics Last lecture Today
Overview Iterative combinational circuits Binary adders
XOR, XNOR, and Binary Adders
Addition and multiplication
Instructor: Alexander Stoytchev
ESE534: Computer Organization
XOR Function Logic Symbol  Description  Truth Table 
Carry-Lookahead, Carry-Select, & Hybrid Adders
Instructor: Alexander Stoytchev
Carry-Lookahead, Carry-Select, & Hybrid Adders
Arithmetic Circuits.
Carry-Lookahead & Carry-Select Adders
XOR, XNOR, and Binary Adders
Number Representation
Instructor: Alexander Stoytchev
Lecture 2 Adders Half adder.
Presentation transcript:

74LS283 4-Bit Binary Adder with Fast Carry Heather Weaver hxw133@psu.edu 897-8551

Pin mappings Pins 12, 14, 3, and 5 are input A (MSB to LSB) Pins 11, 15, 2, and 6 are input B (MSB to LSB) Pins 10, 13, 1, and 4 are the outputs (MSB to LSB) Pin 8 is ground Pin 15 is Vcc Pin 7 is carry in and Pin 9 is carry out

Schematic

Bit Slices Equation for ith bit Si = Ai XOR Bi XOR ci A and B are the inputs C is the carry-in bit Carry occurs 2 ways Generate – the added bits are both 1 Propagate – one add bit is 1 and the carry in bit is 1

Timing of CLA Equations for generate & propagate Generate: gi = Ai AND Bi Propagate: pi = Ai OR Bi Carry-out in terms of generate and propagate: ci+1 = gi AND pi OR ci Each bit slice of CLA has 3 levels of delay One level for generate & propagate signals Two levels for sum of products