The branch instruction B label “label” is an instruction address. Instruction addresses are 32 bits. But branch instructions are immediate format, ONLY 16 BITS !?

How it’s done! x B z x, y, z all have y ! absolute values. ! ! But the quantity z ! z - y is an offset ! (a relative value). If the offset z - y can be represented in 16 bits, then it will fit.

But there’s one more trick.... z and y are valid byte addresses, both word aligned! That means that: z = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00 y = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00 so z - y = xxxxxxxxxxxxxx00 Why waste space representing two bits which are always zero?

But there’s one more trick.... So, shift the difference (z - y) right two bits. That way, if (z - y) fits in 18 bits we can save the offset in 16 bits!

How does the structure work? x B z When we fetch B z, y ! the program counter ! contains the value x. ! z ! That means y = PC + 4. Since offset = (z - y), then PC + 4 + offset = y + z - y, an absolute address!

To calculate the branch address Instruction memory Program counter B Imm z - y shifted right twice Imm 00 Restore the two zeroes 18 bits 14 18 Sign extend to 32 bits PC + 4 4 + Absolute branch address

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend B label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend B label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend B label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Beq rs rt label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Beq rs rt label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Beq rs rt label

Beq rs rt label ? Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze A ALU 4 B ? + 31 + Sgn/Ze extend Beq rs rt label

Procedure call Suppose we have a program that “rings the bell” at 10 different locations in the code. This sort of thing is usually complicated! many, many instructions..... That’s a waste of space can’t we write the “bell code” once and share it?

Procedure call Bal bell back ! ! Bal bell Problem: The back ! return address! Bell ! ! Branch is not ! enough. B back

Return address A We need to tell the subroutine where it should branch back to, i.e., the return address, each time we call it! That means: The return address must be changeable.

Return address B We can’t use B x; X is not changeable we can’t write to the instruction memory... But we can write to: register file data memory So we can write the return address there.

Return address C Suppose we use $31 for example: Jump register $31: Bell ! ! Jr $31 Jump register $31: Read the register file and stores the value into the PC

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Jr $31

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Jr $31

This works (not the best way): ! bell: ! ! ! La $31 x ! B bell ! x: ! Jr $31 ! La $31 y B bell y: !

What’s done?? We just want to get the address La $31 x 2 instructions B bell 1 instruction x: need a label We just want to get the address following the “call” into $31.

La $31 x B bell x: save return reg $31 address in Return address Zero ext. save return address in reg $31 Return address when B bell is fetched Branch logic A ALU 4 B + 31 + Sgn/Ze extend La $31 x B bell x:

The return address The “call” is at “PC”. So, the return address must be PC + 4. But we compute PC + 4. Can we cause PC + 4 to be written to the register file ($31). Yes. Use BAL bell (branch and link) .

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label

Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze extend Bal label

B label … next instr Zero ext. Branch logic A ALU 4 B + 31 + Sgn/Ze A ALU 4 B + 31 + Sgn/Ze extend B label … next instr