332:437 Lecture 16 FSM Synchronizers Synchronization failure Runt pulses Simple synchronizers Synchronizer timing Handshake interface techniques Summary Material from An Engineering Approach to Digital Design, by William I. Fletcher, Englewood Cliffs, NJ: Prentice-Hall 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Synchronization of Systems Needed when merging independent systems on different clocks Problem: System controller needs to know when or within what time frame it can expect input changes from controlled/controlling systems 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Consequences of Synchronization Failure Input Changes missed by system controller Undefined state transitions occur 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Input changing Near Triggering Edge of Clock 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Output Cell in Meta-Stable Condition from “Runt” Pulse 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Meta-Stable Condition of Flip-Flop 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Example Synchronizer Catching Cell Catching cell converts Pulse into level S D C R 7474 RET F/F Q SYSCLK(L) RESET(L) ASYN INPUT(L) CATCHING CELL SYNCHD INPUT(H) +v Q(H) 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Synchronizer with Explicit Reset from System Controller +v ASYN INPUT(H) Q(H) S D C R 7474 RET F/F Q RESET(L) SYSCLK(L) SYSTEM CONTROLLERS OUTPUT DECODER ASYN INPUT(L) CATCHING CELL OR SYNCHD INPUT(H) 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Synching Operation of the Pulse-Catching Circuits 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Synchronizer Timing Considerations May be impractical to increase system clock frequency for synchronization Need to instead catch input pulse & hold it until system controller can service it. fp – frequency of input pulse fc – Clock frequency tp – Period of input pulse tc – Period of Clock First assume that fp < fc 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Synchronizer Based on These Assumptions tp < tc So, tp short & infrequent in relation to system clock State changes of system controller made on rising edge of system clock Time period between falling & rising edge of system clock > system’s setting time 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Bushnell: Digital Systems Design Lecture 16 Missed Short Asynchronous Input Compared to system clock 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Level Synchronization – When tp >> tc Catching level that changes asynchronously with respect to system clock Use same circuit as before, but omit catching cell 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Problem with Asynchronous Inputs Changes in inputs may cause outputs of next state decoder to change during set-up & hold times of flip-flops Causes erratic behavior of present-state register 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Handshake Interface Technique One party stimulates second party Second party signals first to acknowledge receipt of signal First party can now initiate another transaction 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Handshake Between Systems Operating Asynchronously 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Bushnell: Digital Systems Design Lecture 16 Problem Internal input changes in one of the systems being synchronized can cause transient electrical noise on output control lines. May have to design special circuits to sense noise transient and delay action until it damps out. 4/10/2019 Bushnell: Digital Systems Design Lecture 16

Bushnell: Digital Systems Design Lecture 16 Summary Synchronization failure Runt pulses Simple synchronizers Synchronizer timing Handshake interface techniques 4/10/2019 Bushnell: Digital Systems Design Lecture 16