The dal Constraint Tool

Design Constraints: General Questions Who is responsible for entering the Physical and Electrical Constraints for a design? Do you have any homegrown tools to help with the process? What don’t you like about the current process? How do you verify that the constraints in the database match your requirements?

The Design Constraint Problem Creating rules with constraint manager is time consuming, tedious, and error prone How do you know your design Constraints have been implemented properly? How do you check constraints that someone else enters? Are your design constraints portable between designs or do you start over every time? How do you keep your constraints synchronized between the front and back end?

The Solution: dal constraints The Constraint Rules File (CRF) describes Constraint Sets using powerful Macros dal constraints imports the CRF Rules and translates them into valid design constraints Works with existing Constraint Manager and design front ends (AllegroHDL or Orcad) Constraints are always imported into to the ‘backend’ avoiding synchronization issues dal constraints verifies that the design is using all CRF rules

dal constraints… No magic bullets Unfortunately, design constraints cannot be inferred or created out of thin air Constraining a design is a detailed process which must be owned by the engineer Each Interface can require multiple sets of rules that the designer must be aware of dal constraints manages constraints and documents them at the same time dal constraints provides automation in many areas to streamline the process

Quick Comparison… Allegro Constraint Mgr vs dal Constraint

Compressed steps to create a simple RPD in Allegro Constraint Manager

Now create the same RPD using CRF Define one compact RPD MACRO in the CRF! dal constraints does the rest of the work for you

dal Constraints: The Constraint Rules File (CRF)

dal Constraints: The Constraint Rules File (CRF) Constraints are created and edited in the CRF spreadsheet, which travels with design Constraints are defined using powerful macros A macro can create a design rule or tell dal constraints to perform an automated task Macros use advanced bus-aware pattern matches to identify constraint targets Constraint definitions can easily be ported between related designs

dal Constraints: CRF Features Nested Loops and Replication constructs provide maximum efficiency/accuracy Use variables to set tolerances… change the value and all constraints will update Consistent schematic naming conventions make constraint definition easier Use comment ‘#’ to temporarily remove constraint macros Use worksheets to define rational values tolerances instead of over constraining

dal Constraints: CRF MACROS BUILD_STACKUP: Control interface to powerful new dal Stackup tool BUILD_PCS: Define Physical Constraint Sets which can be referenced by ECS BUILD_SCS: Define Space Constraint Sets BUILD_ECS: Define Electrical Constraint Sets, to apply to groups of signals BUILD_DIFF_PAIRS: Intelligently finds all diff_pairs in design

dal Constraints: CRF MACROS ASSIGN_PIN_DIR: Fix improper symbol pin definitions ASSIGN_XNETS: Control assignment of XNETs ASSIGN_VOLTAGE: Assign voltages to nets using pattern recognition ASSIGN_VOLTAGE_FEEDTHRUS: push voltage definitions across series devices PIN_PAIR_PROP: Locate series and parallel termination components

dal Constraints: Relative Propagation Delay (RPD) MACROS ASSIGN_PIN_DELAYS: define Pin Delays for critical components BUILD_SINGLE_RPD: Define Relative Propagation (RPD) rules BUILD_MULTI_RPD: Group related data and strobes into multiple RPDs Use Replicate to create many RPD from one Or use Nested Loops to create many RPD from one

dal Constraints: PCS MACRO Defines Named PHYSICAL CONTRAINT SET Used to constrain the physical attributes of signals on each routing layer Creating by layer rules with Allegro Cmgr is time consuming , and error prone Checking the PCS rules in cmgr is another difficult interactive task dal Stackup creates named PCS for impedance rules extracted from stackup spreadsheet

dal Constraints: PCS MACRO continued Once a named PCS is created it can be applied to a group of signals in an ECS Signals can also be assigned directly using the MEMBERS=> Pattern matches Controlled Impedance rules are defined using PCS Minimum trace widths for power signals can also be defined with PCS Simple Impedance definitions eg: L1,L24=10/7.5:L4,L5,L8,L9,L16,L17,L20,L21=3.7/5

dal Constraints: ECS MACRO Defines ELECTRICAL CONTRAINT SET Use to define a common set of electrical rules to apply to a known set of signals ECS can be also be used top specify the PCS for a set of signals Two main Types, DIFF_PAIR and Single Ended Dynamic and or Static Diff Pair rules are entered with this macro

dal Constraints: ECS Parameters DPAIR and SE Signals IMPEDANCE NUM_VIAS, MATCH_NUM_VIAS MIN_PROP_DLY, MAX_PROP_DLY, MIN_TOTAL_ETCH,MAX_TOTAL_ETCH TOP_MAP_MODE,TOP_VERIFY_SCHEDULE,TOP_SCHEDULE_CONTROL, STUB_LENGTH,MAX_EXPOSED,MAX_PARALLEL,LAYER_SETS

dal Constraints: ECS MACRO for DIFF_PAIRS Static and Dynamic Diff Pair rules may be created with this macro GATHER_CONTROL, STATIC_PHASE, DPA_TOLERANCE, DPA_LENGTH, DPA tracks phase offsets between p/n as signal travels from TX to RX Offsets greater than DPA_TOL must be fixed within DPA_LENGTH . DPA only works when the pin-types for signal endpoints are properly defined Transmitter Pin Delay Skew can also be compensated if provided.

dal Constraints: SCS MACRO Defines SPACING CONTRAINT SET Use to set spacing rules per layer from one class of signal to another Set minimum spacing between High Voltage power rails and low voltage signals Not sure about the SCS… We are trying to keep one set of signals away from another… how do we say which set is which? do we need to have 2 named PCS classes? Do we need more than Line to Line? Line to Shape, Line to Via … This needs more thinking  Create extra spacing between clocks and non-clock signals Set Line to Line, Line to Shape, Line to Via rules

dal Constraints: IDENTIFY_DIFF_PAIRS MACRO Runs exhaustive search to identify and create diff Pairs for the design DIFF_PAIR_POL_MATES=>P:N,T:C,H:L,P:M,!BLANK:_N These are the Character pairs used to search for diff_pairs , The first character in each pair denotes the Non-Inverted Polarity. -If a signal Name has a 'P' in it and we can substitute an 'N' at that position and find a matching signal name we will call that a diff pair -Similarly, if a signal name has a 'T' in it and we substitute a 'C' and find a matching signal name we call that a diff pair (DDR4) c0_ddr4_dqs_t<0>, c0_ddr4_dqs_c<0> -The !BLANK:_N will create a diff_pair for: diff_clk and diff_clk_n or diff1_clk and diff1_n_clk (so we only search _n signals and then try to find matching signal names without the _n FORCE_DIFF_PAIR=>dpair_name=true-sig1:comp-sig1,true-sig2:comp-sig2 Allows the user to identify diff_pairs which would not be identified using the auto DIFF_PAIR_POL_MATES Search

dal Constraints: BUILD_SINGLE_RPD MACRO Defines groups of signals that need to be match length routed Defines rules that Allegro will use to verify the route lengths. Control, Name, Scope , Type, Tolerance, Target and Members Any net that matches the MEMBERS pattern matches but don’t match the NOT_MATCHING patterns will be included in the group Dal, I keep wanting to remind you that we need to check what license features are enabled when we add and check these RPD s so that we don’t end up in the situation we always hit where sometimes the via length was considered and sometimes not. I don’t have a way to define offsets for random signals defined in here either. Pin delays from the source pin and target pins will be included in skew calculations and are usually quite significant.

dal Constraints: SINGLE RPD MACRO with Loops Create Multiple RPDs from RPD Macros within single or nested Loops Here 3 nested loops create 32 RPD groups from the 2 simple RPD macros The MC, SLICE and W are the substitution variables, The variables are pulled from the lists for each iteration of loop !MC! Gets MC0, then MC1, SLICE->M00 then M01,M10 ,M11 !W!-> W0, then W1, W2, W3 The MEMBERS pattern matches are expanded using the values of the loop variables

dal Constraints: BUILD_SINGLE_RPD MACRO with REPLICATE REPLICATE can be used to create multiple RPD groups using simple text substitutions in all of the Macro content REPLICATE txtA=rplcA1,rplcA2…rplcAn [txtB=rplcB1,rplcB2,…rplcBn] NAME, TARGET, MEMBERS and NOT_MATCHING Rules will have text substituted. Dal, I keep wanting to remind you that we need to check what license features are enabled when we add and check these RPD s so that we don’t end up in the situation we always hit where sometimes the via length was considered and sometimes not. I don’t have a way to define offsets for random signals defined in here either. Iterates once for each replacement provided in the REPLICATE statement Simple programming, No Substitution variables are required

dal Constraints: BUILD_MULTI_RPD MACRO Really another type of Loop/Replicate construct Use to split up a large bus into smaller groups along with its control/strobes For example: a ddr bus which has 8 dq per each dqs and dm bus indices have extra inc/dec op… dq[31:0:-8] dqs[3:0:-1] dm[3:0:-1] Dal, I keep wanting to remind you that we need to check what license features are enabled when we add and check these RPD s so that we don’t end up in the situation we always hit where sometimes the via length was considered and sometimes not. I don’t have a way to define offsets for random signals defined in here either. Result 4 RPDS (dq[31:24],dqs3,dm3, dq[23:16],dqs2,dm2… dq[7:0],dqs0,dm0)

dal Constraints: ASSIGN_PIN_DIR MACRO FIX PINUSE properties in database if they are not defined properly in symbols Finds ref-designator endpoints on matching Nets and assigns the PINUSE prop Proper PINUSE definitions are key to using Dynamic Phase Control In Allegro Diff Pair Skew is tracked from an OUTPUT Pin to an INPUT pin

dal Constraints: ASSIGN_PIN_DELAYS MACRO Assign PIN_DELAYS by PART_TYPE or by Reference Designator Specify a .csv file containing pin_delay by pinNum or PinNAME verifies that pin_delays map to valid pins for the selected part Annotating Pin Delays is critical to RPD matching for HighSpeed Memory Pin Delay info is also used in Differential Pair Phase Matching

END Dal Constraint

The dal Stackup Tool

Introducing dal stackup How do you define all the details of a complex stackup in Allegro How do you verify your design stackup against the PCB vendors proposal? dal stackup is the answer! Import the stackup details directly from the Vendors Spreadsheet Compare existing design stackup against the vendor spreadsheet

dal stackup import Supports multiple vendor spreadsheet formats. Custom formats may be added for a reasonable fee. Imports xsection details: smask, core/prepreg thickness, copper weights Extracts vital material parameters per layer including Dk, Df Per layer impedance rules are translated to named Physical Constraint Sets Clearly identifies deviations from proposed stackup with heads up display

END Dal Stackup