ECE 352 Digital System Fundamentals Carry Look-Ahead Adders In this presentation, we will be discussing the carry look-ahead adder.

Optimize The Slow Part: Carry Chain For big adders, the carry chain is very long… Separate the carry and sum logic in a full adder so that we can optimize the carry logic Partial Full Adder (PFA): a full adder without carry logic Modify the carry-chain logic to be a 2-level function instead of a multi-level function Carry Chain We will start with a ripple-carry adder built using partial full adders, or PFAs. This separates the carry-chain logic from the rest of the logic. It’s the carry chain that we want to optimize, because it is the critical path in ripple carry adders. To make the carry-chain faster, we will transform it from a multi-level circuit into a two-level circuit. PFA

Carry Look-Ahead Adder (CLA) As usual, can trade area/power for speed Multi-level logic (ripple carry) reduces area Flattening carry logic increases speed Make carry logic a 2-level function of: Generate (G) “Based on the operand values at just this bit position, will the carry-out for this position be 1 regardless of the carry-in?” Propagate (P) “Based on the operand values at just this bit position, will the carry-out for this position be equal to the carry-in?” In digital logic, we can often get better speed at the expense of a larger and more power-hungry circuit. That’s exactly what we’re going to do here with the carry look-ahead adder, also called a CLA. We will design 2-level carry logic that is a function of the generate and propagate outputs from the partial full adders. Remember that the PFA generate output is a 1 when that adder will produce a carry-out of 1 regardless of what happens with the less significant bits, and that the propagate output is 1 when the adder will produce a carry-out of 1 only if it gets a carry-in of 1.

Ripple-Carry Adder Each carry bit is a multi-level function of the generates and propagates of the lower positions C3 = G2 + P2 C2 = G2 + P2 (G1 + P1 C1) = G2 + P2 (G1 + P1 (G0 + P0 C0)) Ripple-carry adder C3 equation So let’s take another look at a ripple carry adder built from PFAs. Here we show the multi-level carry logic for a 4-bit ripple-carry adder. C0 is the carry-in to the whole adder, and G0 and P0 come from the PFA at the least significant bit: bit 0. Based on the diagram, the logic for C1, the carry-in to bit 1, is G0 + P0·C0. Bit 1 has a carry-in if bit 0 generates a carry, or if bit 0 propagates its carry-in. Now let’s look at C3—the carry-in to bit 3. C3 will be 1 if bit 2 generates a carry (G2 is 1) or if bit 2 propagates a carry (P2 is 1) and its carry-in C2 is 1. But C2 is not an input to the adder. It’s the result of the carry calculation for the previous bit position. If we substitute for C2 in the equation, we see that C3 also depends on the value of C1, along with the generate and propagate signals from position 1. If we then substitute for C1, we find that C3 also depends on the value of C0, along with the generate and propagate signals from position 0. At this point, we actually have the multi-level equation that describes C3 for a ripple-carry adder as a function of the generate and propagate signals from the PFAs and the adder’s carry-in C0.

Carry Look-Ahead Adder Each carry bit is a two-level function of the generates and propagates of the lower positions Now let’s replace that ripple-carry chain with a 2-level function of the generates, propagates, and carry-in C0. Here’s the diagram of the resulting logic, showing how it connects to the PFAs. Just like before, the Gs and Ps produced by the PFAs are inputs to the carry-chain logic, and the carry bits are outputs of the carry-chain logic. The difference is in the logic used to calculate those carry bits.

Getting There Algebraically “Flatten” the ripple-carry equation to two levels C3 = G2 + P2 (G1 + P1 (G0 + P0 C0)) = G2 + P2 G1 + P2 P1 (G0 + P0 C0) = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 Carry look-ahead adder C3 equation Let’s focus on the carry-chain itself. This logic is the result of distributing variables into the parentheses of the ripple-carry equation, flattening it to be a 2-level sum-of-products. We will again look at C3, and we will start from the ripple-carry equation. We distribute P2 into the parentheses, then we distribute P1 into the remaining parentheses to create a two-level equation for C3 in terms of the Gs, Ps, and carry-in C0. This equation is in fact the carry look-ahead equation for C3, which matches the highlighted part of the diagram below.

Carry Look-Ahead Logic You do not need to memorize the function for each carry bit! Instead, remember what generate and propagate mean, and how MATH works C3 C0 A3 A2 A1 A0 + B3 B2 B1 B0 C3 = G2 + G1 P2 + G0 P2 P1 + C0 P2 P1 P0 Fortunately, you really don’t have to memorize the logic for each bit of the carry look-ahead block. Instead, remember what the words “generate” and “propagate” mean. For example, if we look at a four-bit addition of operands A and B, and we want to know the carry look-ahead equation for C3, we just think about all the possible ways that C3 might be 1, and enumerate them in an equation. So, C3 will be 1 if position 2 generates a carry, or if a carry that is generated at any point earlier in the addition would be propagated to C3. Don’t forget to include a term for the case where a carry at C0 is propagated all the way to C3. Note that there is a term in the equation for every less-significant position that could generate a carry, and that term includes all the propagates needed to get that carry to the position we’re looking at. You can use this same process to determine the carry look-ahead equation for any carry bit. C3 will be 1 if bit 2 generates a carry, or if bit 1 generates a carry and it propagates at bit 2, or if bit 0 generates a carry and it propagates at bit 1 and bit 2, or if the carry-in at the least-significant bit is 1 and it propagates at bit 0 and bit 1 and bit 2.

Extending Carry Look-Ahead Higher carry indices require more AND gates and a bigger OR gate There is a practical limit on the size of gates… How can we make wider adders? Hierarchy! Add look-ahead outputs indicating if the 4-bit group of PFAs generate or propagate a carry to the next group A higher-level look-ahead block uses group generates and propagates to determine carry-ins for each group Same idea as before, but for a group of bits “Does this GROUP generate a carry?” “Does this GROUP propagate a carry?” How far can we take this? Do we make a two-level equation for C63—the carry-in to the 63rd bit of a 64-bit adder? The answer is “No”. That would require an enormous OR gate and many AND gates, some of which are also overly large. We really can’t make gates that wide. So, if we want to make a large carry look-ahead adder, we need to instead use hierarchy. We compute, for a group of bits (usually four), whether that group as a whole will generate a carry out of the group, or propagate a carry all the way through the group. These group generate and group propagate signals are then used by another look-ahead block to determine the carry-ins for each group. The words “generate” and “propagate” have the same meaning as before, but for these new signals, they apply to the GROUP of bits, rather than an individual position.

Extending Carry Look-Ahead Replace C4 output with a group generate output GG, and a group propagate output PG GG is 1 if the group will generate a carry PG is 1 if the group will propagate the carry Here’s the carry logic for a 4-bit CLA that we looked at previously. Now we’ll replace the C4 logic with logic that outputs the group generate G_G and group propagate P_G. How do we know if the group generates a carry? If any of its positions generate a carry which is propagated out of the group. How do we know if the group propagates a carry? If a carry-in would be propagated through every position in the group.

16-Bit Carry Look-Ahead Adder Entire 4-bit carry look-ahead adders (instead of PFAs) are connected to a top-level look-ahead Top-level look-ahead produces carry-in bits for each 4-bit CLA block based on group generates and propagates of the lower CLA blocks 4-bit look-ahead block Now let’s use our modified look-ahead block to create a 16-bit CLA out of four 4-bit CLAs. The 4-bit CLAs are arranged along the bottom, with an additional look-ahead block that connects them. This is a little hard to see, so let’s zoom in on the right half of the diagram. 4-bit carry look-ahead adders

16-Bit Carry Look-Ahead Adder Entire 4-bit carry look-ahead adders (instead of PFAs) are connected to a top-level look-ahead Top-level look-ahead produces carry-in bits for each 4-bit CLA block based on group generates and propagates of the lower CLA blocks 4-bit look-ahead block C4 = GG0 + PG0C0 This image shows the lower two 4-bit CLAs, where we can also see inside the one on the left. Both of them have the same internal logic, with a look-ahead block that provides the carry computation for each position based on the generates and propagates computed by the PFAs. The group generates from each 4-bit CLA are connected to the generate and propagate inputs of the top look-ahead block. The top look-ahead block computes the value for C4 (and C8 and C12), based on the value of C0 and the G_Gs and P_Gs of the four CLAs. C4 will be a 1 if G_G0 is a 1, or if P_G0 is a 1 and C0 is a 1. In words, there will be a carry into the second 4-bit CLA if the first 4-bit CLA generates a carry, or it is propagating and the carry input to the whole adder is 1. Seem familiar?

16-Bit Carry Look-Ahead Adder Entire 4-bit carry look-ahead adders (instead of PFAs) are connected to a top-level look-ahead Top-level look-ahead produces carry-in bits for each 4-bit CLA block based on group generates and propagates of the lower CLA blocks 4-bit look-ahead block The look-ahead block on top is exactly the same structure as the one inside the 4-bit CLAs, except it has an additional carry bit calculation instead of the group generate and propagate outputs. It computes signal C12, the carry-in to the leftmost 4-bit CLA by using the equation shown, which at this point should look very familiar. The C12 signal for the 16-bit CLA is used inside the leftmost 4-bit CLA as its signal C0 – that’s how hierarchy works. All of the 4-bit CLAs are identical; we make them compute different parts of the addition based on which signals we connect them to. C12 = GG2 + PG2GG1 + PG2PG1GG0 + PG2PG1PG0C0

Extending Further… We can make even larger carry look-ahead adders by adding more levels of hierarchy Build a 64-bit CLA with four 16-bit CLAs plus another look-ahead block Each 16-bit CLA would need a group generate and a group propagate output in its top-level look-ahead Does this group of 16 bits generate a carry? Does this group of 16 bits propagate a carry? Hierarchical CLA carry chain is no longer two-level But far fewer levels than if it were a ripple-carry adder! CLA delay grows more slowly with operand size What if we want to make an even bigger CLA? We would add even more levels of hierarchy. Whenever we have more than one level of look-ahead logic, the carry-chain is no longer just two levels. Carry calculation has to go through multiple two-level look-ahead blocks. However, the delay grows much more slowly with an increase in carry look-ahead adder size than it does with an increase in ripple-carry adder size.

ECE 352 Digital System Fundamentals Carry Look-Ahead Adders This concludes our video on carry look-ahead adders. Comparing carry look-ahead adders and ripple-carry adders highlights the idea of tradeoffs between area and speed – a common concept in digital logic design.