EE 5340 Semiconductor Device Theory Lecture 23 - Fall 2003 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc L 23 Nov 11

Ideal 2-terminal MOS capacitor/diode conducting gate, area = LW Vgate -xox SiO2 y L silicon substrate tsub Vsub x L 23 Nov 11

Band models (approx. scale) metal silicon dioxide p-type s/c Eo qcox ~ 0.95 eV Eo Eo qcSi= 4.05eV qfm= 4.1 eV for Al Ec qfs,p Eg,ox ~ 8 eV EFm Ec EFp EFi Ev Ev L 23 Nov 11

Flat band condition (approx. scale) SiO2 p-Si q(fm-cox)= 3.15 eV q(cox-cSi)=3.1eV Ec,Ox qffp= 3.95eV EFm Ec Eg,ox~8eV EFi EFp Ev Ev L 23 Nov 11

MOS surface states** p- substr = n-channel L 23 Nov 11

n-substr accumulation (p-channel) Fig 10.7a* L 23 Nov 11

n-substrate depletion (p-channel) Fig 10.7b* L 23 Nov 11

n-substrate inversion (p-channel) Fig 10.7* L 23 Nov 11

Values for gate work function, fm L 23 Nov 11

Values for fms with metal gate L 23 Nov 11

Values for fms with silicon gate L 23 Nov 11

Typical fms values Fig 10.15* fms (V) NB (cm-3) L 23 Nov 11

Flat band with oxide charge (approx. scale) SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) q(fm-cox) Ex Eg,ox~8eV EFm Ec EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev L 23 Nov 11

Flat-band parameters for n-channel (p-subst) L 23 Nov 11

Flat-band parameters for p-channel (n-subst) L 23 Nov 11

Inversion for p-Si Vgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Depl Reg Acceptors Vsub = 0 L 23 Nov 11

Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG = VTh Assume ns = 0 for VG < VTh Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh Cd,min = eSi/xd,max for VG > VTh Assume ns > 0 for VG > VTh L 23 Nov 11

MOS Bands at OSI p-substr = n-channel Fig 10.9* 2q|fp| qfp xd,max L 23 Nov 11

Computing the D.R. W and Q at O.S.I. Ex Emax x L 23 Nov 11

Calculation of the threshold cond, VT L 23 Nov 11

Equations for VT calculation L 23 Nov 11

Fully biased n-MOS capacitor VG Channel if VG > VT VS VD EOx,x> 0 n+ e- e- e- e- e- e- n+ p-substrate Vsub=VB Depl Reg Acceptors y L L 23 Nov 11

MOS energy bands at Si surface for n-channel Fig 8.10** L 23 Nov 11

Computing the D.R. W and Q at O.S.I. Ex Emax x L 23 Nov 11

Q’d,max and xd,max for biased MOS capacitor Fig 8.11** xd,max (mm) L 23 Nov 11

Fully biased n- channel VT calc L 23 Nov 11

n-channel VT for VC = VB = 0 Fig 10.20* L 23 Nov 11

Project Hints: rp rpc rj rn rnc Project due date changed to November 18. L 23 Nov 11

References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986 L 23 Nov 11