Ian Reynolds, Obasi Onuoha, Phillip Cherner 6.175 Final Project Ian Reynolds, Obasi Onuoha, Phillip Cherner

Cache Coherent 2 Core Processor

Progress: All of Part 1 Made adjustments to the blocking cache without much issue Some issues with LHUSM Mostly due to silly errors

Progress: Part 2 Standard MessageFIFO Message Router Used a round-robin ordering to prevent starvation Parent Protocol Processor Split parentResp into 2 rules to account for realistic memory Integrating the memory hierarchy Failed

Difficulties Encountered Cache Starvation Solved by using a round-robin message router Parent Protocol Processor Several issues with scheduling The binary nature of messageFIFO’s caused some issues Tags Tags being out of sync and causing MSI states to be invalid

Difficulties Continued Integrating the memory hierarchy Everything broke Many, many hours spent attempting to debug We think the error is resultant from improper handling of downgrade requests Given that, we were still unable to find the source of the problem

Contributions Most of the design work was done in sequence One person typing, the other sanity checking and watching for bugs We rotated typing The debugging was largely done in parallel People attempting different solutions on different terminals

Improvements to the Class FPGA infrastructure Took several compile attempts with no changes to source code before it worked Compile times Extremely long; much time is wasted staring at terminal Pacing The pacing is not uniform There are some difficulty spikes and drops throughout

Final Thoughts Overall, a very good class The final project was very interesting Slides could be updated Learned quite a bit Would recommend