Systems Architecture I September 4, 1997 Systems Architecture I (CS 281-001) Lecture 3b: Review of Sequential Logic Circuits Jeremy R. Johnson Oct. 1, 2001 Oct. 1, 2001 Systems Architecture I

Systems Architecture I September 4, 1997 Introduction Objective: To understand how data can be stored in a computer. Sequential vs. Combinational Logic Flip-flop Timed flip-flop Implementing computer memory Review of the simple computer model References: Dewdney, The New Turing Omnibus (Chapter 38 and 48) and Sec. B4-B7 of the text. Oct. 1, 2001 Systems Architecture I

Combinational vs. Sequential Circuits September 4, 1997 Combinational vs. Sequential Circuits A combinational circuit is a logic circuit without any loops. The same outputs are always computed for the same inputs. A sequential circuit contains two-state memory elements which can remember the state over time. The outputs depend on both the inputs and the current state. The state changes over time which is marked off in discrete steps by pulses emanating from a clock. The pulses coordinate activity. Oct. 1, 2001 Systems Architecture I

Systems Architecture I September 4, 1997 Flip-Flop (SR-Latch) A sequential logic circuit with two states. The two states are (Q=0, Q’=1) and (Q=1,Q’=0) Provided the input (R = 0, S = 0) is not allowed, the flip-flop can only be in one of these two states. Q Q’ S R Oct. 1, 2001 Systems Architecture I

Systems Architecture I September 4, 1997 Flip-Flop States The state (Q=0,Q’=1) corresponds to storing a 0. The state (Q=1,Q’=0) corresponds to storing a 1. If S (set) is 1, then the state is set to 1. If R (reset) is 1, then the state is set to 0. If R & S are 1, the state does not change. Old Q R S Q’ Next Q 0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 0 1 0 1 Q Q’ S R Oct. 1, 2001 Systems Architecture I

Systems Architecture I September 4, 1997 Flip-Flop States The transitions of the flip-flop are conveniently described in the following state transition diagram (finite state machine). The arcs are labeled by the RS inputs that cause the transition. In the diagram, state 0 is when Q = 0 and Q’ = 1, and state 1 is when Q = 1 and Q’ = 0. 1 10 01 11 Oct. 1, 2001 Systems Architecture I

Systems Architecture I A Clocked Flip-Flop R Q clock Q’ S Oct. 1, 2001 Systems Architecture I

Systems Architecture I N-bit Register A state variable containing N-bits Built from an array of N flip-flops State changes when load selected and the clock is high Oct. 1, 2001 Systems Architecture I

Systems Architecture I N-bit Register R Q S Q’ X1 R Q S Q’ X2 load clock Oct. 1, 2001 Systems Architecture I

Systems Architecture I Memory Cell read = 1/write = 0 R Q S Q’ input output select Oct. 1, 2001 Systems Architecture I

Systems Architecture I Memory Input N = 2k words each l bits Inputs k address bits l data-in bits (for write) flag to select read /write Outputs l data-out bits (for read) Built from N  l array of memory cells input, output, flag, select Decoder used to decode address Memory Address Output R/W Oct. 1, 2001 Systems Architecture I

Systems Architecture I Memory D e c o d r input output read/write 1 7 Oct. 1, 2001 Systems Architecture I

Systems Architecture I September 4, 1997 LOAD READ/ WRITE MAR Memory LOAD PC INC MUX s 0 1 2 3 LOAD IR(C) IR(O) LOAD MUX MBR 1 s Decoder 1 2 3 MUX LOAD q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 x13 x12 x11 x10 x9 x8 x7 x6 AC x1 x2 x3 x4 x5 s MUX 1 ALU s LOAD AD t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 INC CLEAR Decoder T Oct. 1, 2001 Systems Architecture I