ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Lecture #8

CPU Registers Read: MC9S12C32 Device User Guide V01.14 HCS12 Microcontrollers: MC9S12C128 Rev 01.23

MC9S12C Microcontroller Covered in Lecture 5: Quick Introduction to Microcontroller Subsystems Microcontroller Registers Microcontroller Modes (Single chip, Extended, etc..) EVBU Memory Maps Covered in this section: HCS12 CPU (Note: the Central Processing Unit (CPU) is the “core” of the microcontroller where instructions are executed)

Circuits to process instructions CPU Registers Used to: The HCS12 CPU contains: Circuits to process instructions CPU Registers Used to: Perform Arithmetic Logic Operations and etc. (Note: HCS12 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations)

Accumulators A, B, and D A & B are: 8-bit registers Can be used for 8-bit math operations ( Note: This is why A & B are called “Accumulators”) Can also be used for 8-bit binary logic, comparisons, memory transfers, etc… Can be used for accumulator offsets in indexed addressing D is: 16-bit register Cannot be used when A or B is in use Can be used for 16-bit math in conjunction with Index X & Y Can be used for 16-bit memory transfers, comparisons, etc.. Index Registers X & Y Can be used for 16-bit math just like Accumulator D Mainly used for addressing memory in Indexed mode (Note: Indexed addressing mode will be covered in a later section) Program Counter (PC) Contains the address of the next instruction to be executed Can be used as index register in indexed addressing Stack Pointer (SP) Contains the address of the last stack location used (1 greater than the currently available location)

Example : Write a program to add the numbers 1010 and 1110. Example Problem 1 Example : Write a program to add the numbers 1010 and 1110. Solution ORG $1000 LDAA #$0A *Puts number $0A in acc. A LDAB #$0B *Puts number $0B in acc. B ABA *Adds acc. B to acc. A STAA $00 *Stores results in address $00 SWI *Software interrupt END LDAB and LDAA use immediate addressing mode STAA uses direct addressing mode

HCS12 CPU STACK AND STACK POINTER Stack is a region of RAM which may be used for temporary data storage during: programming or interrupt. For Expanded Mode (MON12 in use): Stack location is $0E5F-$0E00 Upon reset, the stack pointer must be initialized. MON12 loads stack pointer with $0E5F and has reserved memory locations $0E5E-$0E00 for the stack, creating 95 bytes of storage. When MON12 is not in use, the user must load stack pointer with appropriate address using LDS instruction: LDS #$0E5F (or appropriate memory location) User must determine stack location and ensure it does not conflict with other resources?

HCS12 CPU STACK POINTER Interrupt can be recognized at any time if it is enabled by its: Local mask, if any (e.g. in Timers, SCI, ADC and etc), and Global mask bit in CCR (e.g. I and X bits). Once interrupt source is recognized, CPU responds at completion of instruction being executed. Content of CPU Registers are pushed into Stack. Interrupt latency varies according to number of cycles required to complete current instruction. After CCR value is stacked, interrupt vector for highest priority pending source is fetched If IRQ is pending: I bit is set to inhibit further interrupts from Maskable interrupts. If XIRQ is pending: I bit and X bit are set to inhibit further interrupts from both Maskable and Non-maskable interrupts. Execution continues at address specified in corresponding interrupt vector. At end of interrupt service routine, return-from-interrupt (RTI) instruction is executed.

Stack Register will contain #$0E5F RTI: Contents of CPU Registers saved in Stack are pulled from Stack in reverse order and put back in their respective registers. Normal program execution will resume at address contained in Program Counter Register Stack Register will contain #$0E5F RTI: LEGEND: RTN = ADDRESS OF NEXT INSTRUCTION IN MAIN ROGRAM TO BE EXECUTED UPON RETURN FROM SUBROUTINE RTNHI = MOST SIGNIFICANT BYTE OF RETURN ADDRESS RTNLO = LEAST SIGNIFICANT BYTE OF RETURN ADDRESS X,YHI = MOST SIGNIFICANT BYTE OF X OR Y INDEX REGISTER X,YLO = LEAST SIGNIFICANT BYTE OF X OR Y INDEX REGISTER

Execution of Jump To Subroutine (JSR) and Branch To Subroutine (BSR) instructions causes: Contents of Program Counter (PC) to be pushed onto Stack. Subroutine is executed Last instruction code executed in subroutine is Return from Subroutine (RTS) instruction. RTS causes return address to be pulled from Stack and put in Program Counter CPU uses address in PC to determine where it should continue program execution in main program after JSR or BSR instruction. JSR or BSR: RTS:

S X H I N Z V C MC9S12C CONDITION CODE REGISTER ARITHMETIC BITS Reflect results of instruction execution C – Carry/Borrow from MSB unsigned arithmetic: 10101001 #$4A - #$CE 11000100 101101101 V – 2’s complement overflow indication signed arithmetic (+$7F to -$80) Z – Zero result N – Negative (follows MSB of result) H – Half Carry from bit 3 to bit 4 ADD operations only: MASKING BITS S – Disables STOP instruction when set. X – Masks XIRQ Request when set. set by hardware reset, cleared by software set by unmasked XIRQ See page 116 of Technical Data I – Masks interrupt request from all IRQ level sources (both external and internal) when set. set by masked I level request or unmasked XIRQ level request. 7 0 01001111 +00001000 01010111 H will be set to 1

Example 3 from Lecture 4: - 8510 - 9010=-17510 8510 = 5516 = 0101 01012 1010 1010 = 1’s comp. of 5516 1010 1011 = 2’s comp. of 5516 9010 = 5A16 = 0101 10102 1010 0101 = 1’s comp. of 5A16 1010 0110 = 2’s comp. of 5A16 1010 1011 = (2’s comp. of 5516) 1010 0110 = (2’s comp. of 5A16) ------------- 1 0101 0001 = +5116 = +8110 V bit will be set. C bit will be set.

QUESTIONS???