ESE534: Computer Organization

Slides:



Advertisements
Similar presentations
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 14: March 19, 2014 Compute 2: Cascades, ALUs, PLAs.
Advertisements

Chapter 4 -- Modular Combinational Logic. Decoders.
Comparator.
Caltech CS184a Fall DeHon1 CS184a: Computer Architecture (Structures and Organization) Day3: October 2, 2000 Arithmetic and Pipelining.
Fast Adders See: P&H Chapter 3.1-3, C Goals: serial to parallel conversion time vs. space tradeoffs design choices.
EECS Components and Design Techniques for Digital Systems Lec 17 – Addition, Subtraction, and Negative Numbers David Culler Electrical Engineering.
ECE C03 Lecture 61 Lecture 6 Arithmetic Logic Circuits Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
Chapter # 5: Arithmetic Circuits Contemporary Logic Design Randy H
Lecture 8 Arithmetic Logic Circuits
Design of Arithmetic Circuits – Adders, Subtractors, BCD adders
Penn ESE Spring DeHon 1 ESE : Computer Organization Day 3: January 17, 2007 Arithmetic and Pipelining.
Chapter 5 Arithmetic Logic Functions. Page 2 This Chapter..  We will be looking at multi-valued arithmetic and logic functions  Bitwise AND, OR, EXOR,
CALTECH CS137 Winter DeHon 1 CS137: Electronic Design Automation Day 9: January 30, 2006 Parallel Prefix.
Chapter # 5: Arithmetic Circuits
Chapter 6-1 ALU, Adder and Subtractor
5-1 Programmable and Steering Logic Chapter # 5: Arithmetic Circuits.
Computing Systems Designing a basic ALU.
1 Lecture 12 Time/space trade offs Adders. 2 Time vs. speed: Linear chain 8-input OR function with 2-input gates Gates: 7 Max delay: 7.
1 Arithmetic I Instructor: Mozafar Bag-Mohammadi Ilam University.
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 3: February 3, 2014 Arithmetic Work preclass exercise.
Caltech CS184 Winter DeHon CS184a: Computer Architecture (Structure and Organization) Day 3: January 10, 2005 Arithmetic and Pipelining.
1 Carry Lookahead Logic Carry Generate Gi = Ai Bi must generate carry when A = B = 1 Carry Propagate Pi = Ai xor Bi carry in will equal carry out here.
CS 151: Digital Design Chapter 4: Arithmetic Functions and Circuits
ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill.
Lecture #23: Arithmetic Circuits-1 Arithmetic Circuits (Part I) Randy H. Katz University of California, Berkeley Fall 2005.
Penn ESE534 Spring DeHon 1 ESE534: Computer Organization Day 3: January 25, 2010 Arithmetic Work preclass exercise.
Caltech CS184 Winter DeHon CS184a: Computer Architecture (Structure and Organization) Day 3: January 13, 2003 Arithmetic and Pipelining.
Gunjeet Kaur Dronacharya Group of Institutions. Binary Adder-Subtractor A combinational circuit that performs the addition of two bits is called a half.
1 Arithmetic Building Blocks Today: Signed ArithmeticFirst Hour: Signed Arithmetic –Section 5.1 of Katz’s Textbook –In-class Activity #1 Second Hour: Adder.
CDA3101 Recitation Section 5
Computer Arthmetic Chapter Four P&H.
Addition and Subtraction
Combinational Circuits
Somet things you should know about digital arithmetic:
Lecture 12 Logistics Last lecture Today HW4 due today Timing diagrams
Lecture Adders Half adder.
CS2100 Computer Organisation
Addition and multiplication
Digital Systems Section 8 Multiplexers. Digital Systems Section 8 Multiplexers.
Summary Half-Adder Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out.
Combinational Circuits
ECE 331 – Digital System Design
CSE Winter 2001 – Arithmetic Unit - 1
Topic 3b Computer Arithmetic: ALU Design
Lecture 14 Logistics Last lecture Today
King Fahd University of Petroleum and Minerals
Arithmetic Functions & Circuits
Arithmetic Circuits (Part I) Randy H
Instructor: Alexander Stoytchev
Topic 3b Computer Arithmetic: ALU Design
Digital Systems Section 12 Binary Adders. Digital Systems Section 12 Binary Adders.
CS 140 Lecture 14 Standard Combinational Modules
UNIVERSITY OF MASSACHUSETTS Dept
Overview Part 1 – Design Procedure Part 2 – Combinational Logic
Arithmetic and Decisions
CSE 140 Lecture 14 Standard Combinational Modules
Addition and multiplication
Instructor: Mozafar Bag-Mohammadi University of Ilam
Instructor: Alexander Stoytchev
Lecture 14 Logistics Last lecture Today
Overview Iterative combinational circuits Binary adders
Addition and multiplication
ECE 352 Digital System Fundamentals
ESE534: Computer Organization
Instructor: Alexander Stoytchev
Combinational Circuits
74LS283 4-Bit Binary Adder with Fast Carry
Lecture 9 Digital VLSI System Design Laboratory
Lecture 2 Adders Half adder.
Presentation transcript:

ESE534: Computer Organization Day 3: January 23, 2012 Arithmetic Work preclass exercise Penn ESE534 Spring2012 -- DeHon

Last Time Boolean logic  computing any finite function Saw gates…and a few properties of logic Penn ESE534 Spring2012 -- DeHon

Today Addition organization design space parallel prefix Penn ESE534 Spring2012 -- DeHon

Why? Start getting a handle on Arithmetic underlies much computation Complexity Area and time Area-time tradeoffs Parallelism Regularity Arithmetic underlies much computation grounds out complexity Penn ESE534 Spring2012 -- DeHon

Preclass Penn ESE534 Spring2012 -- DeHon

Circuit 1 Can the delay be reduced? How? To what? Penn ESE534 Spring2012 -- DeHon

Tree Reduce AND Penn ESE534 Spring2012 -- DeHon

Circuit 2 Can the delay be reduced? Penn ESE534 Spring2012 -- DeHon

Circuit 3 Can the delay be reduced? Penn ESE534 Spring2012 -- DeHon

Brute Force Multi-Output AND How big? ~38 here … in general about N2/2 Penn ESE534 Spring2012 -- DeHon

Brute Force Multi-Output AND Can we do better? Penn ESE534 Spring2012 -- DeHon

Circuit 4 Can the delay be reduced? Penn ESE534 Spring2012 -- DeHon

Addition Penn ESE534 Spring2012 -- DeHon

Example: Bit Level Addition Base 2 example Work together C: 11011010000 A: 01101101010 B: 01100101100 S: 1010010110 C: 1011010000 A: 01101101010 B: 01100101100 S: 010010110 C: 11011010000 A: 01101101010 B: 01100101100 S: 11010010110 C: 0 A: 01101101010 B: 01100101100 S: C: 011010000 A: 01101101010 B: 01100101100 S: 10010110 A: 01101101010 B: 01100101100 S: C: 11010000 A: 01101101010 B: 01100101100 S: 0010110 C: 000 A: 01101101010 B: 01100101100 S: 10 C: 00 A: 01101101010 B: 01100101100 S: 0 C: 0000 A: 01101101010 B: 01100101100 S: 110 C: 10000 A: 01101101010 B: 01100101100 S: 0110 C: 1010000 A: 01101101010 B: 01100101100 S: 010110 C: 010000 A: 01101101010 B: 01100101100 S: 10110 Penn ESE534 Spring2012 -- DeHon

Addition Base 2 A = an-1*2(n-1)+an-2*2(n-2)+... a1*21+ a0*20 = S (ai*2i) S=A+B What is the function for si … carryi? si= carryi xor ai xor bi carryi = ( ai-1 + bi-1 + carryi-1) 2 = ai-1*bi-1+ai-1*carryi-1 + bi-1*carryi-1 = MAJ(ai-1,bi-1,carryi-1) Penn ESE534 Spring2012 -- DeHon

Ripple Carry Addition Shown operation of each bit Often convenient to define logic for each bit, then assemble: bit slice Penn ESE534 Spring2012 -- DeHon

Ripple Carry Analysis Area: O(N) [6n] Delay: O(N) [2n] What is area and delay for N-bit RA adder? [unit delay gates] Penn ESE534 Spring2012 -- DeHon

Can we do better? Lower delay? Penn ESE534 Spring2012 -- DeHon

Important Observation Do we have to wait for the carry to show up to begin doing useful work? We do have to know the carry to get the right answer. How many values can the carry take on? Penn ESE534 Spring2012 -- DeHon

Idea Compute both possible values and select correct result when we know the answer Penn ESE534 Spring2012 -- DeHon

Preliminary Analysis Delay(RA) --Delay Ripple Adder Delay(RA(n)) = k*n [k=2 this example] Delay(RA(n)) = 2*(k*n/2)=2*DRA(n/2) Delay(P2A) -- Delay Predictive Adder Delay(P2A)=DRA(n/2)+D(mux2) …almost half the delay! Penn ESE534 Spring2012 -- DeHon

Recurse If something works once, do it again. Use the predictive adder to implement the first half of the addition Penn ESE534 Spring2012 -- DeHon

Recurse Penn ESE534 Spring2012 -- DeHon

Recurse Redundant (can share) N/4 Penn ESE534 Spring2012 -- DeHon

Recurse If something works once, do it again. Use the predictive adder to implement the first half of the addition Delay(P4A(n))= Delay(RA(n/4)) + D(mux2) + D(mux2) Delay(P4A(n))=Delay(RA(n/4))+2*D(mux2) Penn ESE534 Spring2012 -- DeHon

Recurse By know we realize we’ve been using the wrong recursion should be using the Predictive Adder in the recursion Delay(PA(n)) = Delay(PA(n/2)) + D(mux2) Every time cut in half…? How many times cut in half? Delay(PA(n))=log2(n)*D(mux2)+C C = Delay(PA(1)) if use FA for PA(1), then C=2 Penn ESE534 Spring2012 -- DeHon

Another Way (Parallel Prefix) Penn ESE534 Spring2012 -- DeHon

CLA Think about each adder bit as a computing a function on the carry in C[i]=g(c[i-1]) Particular function f will depend on a[i], b[i] g=f(a,b) Penn ESE534 Spring2012 -- DeHon

Functions What are the functions g(c[i-1])? g(c)=carry(a=0,b=0,c) Penn ESE534 Spring2012 -- DeHon

Functions What are the functions g(c[i-1])? g(x)=1 Generate a[i]=b[i]=1 g(x)=x Propagate a[i] xor b[i]=1 g(x)=0 Squash a[i]=b[i]=0 Penn ESE534 Spring2012 -- DeHon

Combining Want to combine functions Compute c[i]=gi(gi-1(c[i-2])) Compute compose of two functions What functions will the compose of two of these functions be? Same as before Propagate, generate, squash Penn ESE534 Spring2012 -- DeHon

Compose Rules (LSB MSB) GG GP GS PG PP PS SG SP SS [work on board] Penn ESE534 Spring2012 -- DeHon

Compose Rules (LSB MSB) GG = G GP = G GS = S PG = G PP = P PS = S SG = G SP = S SS = S Penn ESE534 Spring2012 -- DeHon

Combining Do it again… Combine g[i-3,i-2] and g[i-1,i] What do we get? Penn ESE534 Spring2012 -- DeHon

Reduce Tree Penn ESE534 Spring2012 -- DeHon

Reduce Tree Sq=/A*/B Gen=A*B Sqout=Sq1+/Gen1*Sq0 Genout=Gen1+/Sq1*Gen0 Penn ESE534 Spring2012 -- DeHon

Reduce Tree Sq=/A*/B Gen=A*B Sqout=Sq1+/Gen1*Sq0 Genout=Gen1+/Sq1*Gen0 Delay and Area? Penn ESE534 Spring2012 -- DeHon

Reduce Tree A(Encode)=2 Sq=/A*/B Gen=A*B D(Encode)=1 A(Combine)=4 D(Combine)=2 A(Carry)=2 D(Carry)=1 Sq=/A*/B Gen=A*B Sqout=Sq1+/Gen1*Sq0 Genout=Gen1+/Sq1*Gen0 Penn ESE534 Spring2012 -- DeHon

Reduce Tree: Delay? D(Encode)=1 D(Combine)=2 D(Carry)=1 Delay = 1+2log2(N)+1 Penn ESE534 Spring2012 -- DeHon

Reduce Tree: Area? A(Encode)=2 A(Combine)=4 A(Carry)=2 Area= 2N+4(N-1)+2 Penn ESE534 Spring2012 -- DeHon

Reduce Tree: Area & Delay Area(N) = 6N-2 Delay(N) = 2log2(N)+2 Penn ESE534 Spring2012 -- DeHon

How Relate? Penn ESE534 Spring2012 -- DeHon

Need Need PG[i:0] forall i Penn ESE534 Spring2012 -- DeHon

Intermediates Can we compute intermediates efficiently? Penn ESE534 Spring2012 -- DeHon

Intermediates Share common terms Penn ESE534 Spring2012 -- DeHon

Reduce Tree While computing PG[N,0] compute many PG[I,j]’s PG[1,0], PG[3,0], PG[7,0] …. Penn ESE534 Spring2012 -- DeHon

Prefix Tree While computing PG[N,0] only get How fillin holes? Penn ESE534 Spring2012 -- DeHon

Prefix Tree Look at Symmetric stage (with respect to middle=PG[N,0] stage) and combine to fillin Penn ESE534 Spring2012 -- DeHon

Prefix Tree Penn ESE534 Spring2012 -- DeHon

Prefix Tree Penn ESE534 Spring2012 -- DeHon

Prefix Tree Bring in Carry and compute each intermediate carry-in Penn ESE534 Spring2012 -- DeHon

Prefix Tree Note: prefix-tree is same size as reduce tree Always matched same number of elements in symmetric stage Penn ESE534 Spring2012 -- DeHon

Parallel Prefix Area and Delay? Roughly twice the area/delay Area= 2N+4N+4N+2N = 10N Delay = 4log2(N)+2 Conclude: can add in log time with linear area. Penn ESE534 Spring2012 -- DeHon

Parallel Prefix Important Pattern Applicable any time operation is associative Or can be made assoc. as in MAJ case Examples of associative functions? Non-associative? Function Composition is always associative Penn ESE534 Spring2012 -- DeHon

Note: Constants Matter Watch the constants Asymptotically this Carry-Lookahead Adder (CLA) is great For small adders can be smaller with fast ripple carry larger combining than 2-ary tree mix of techniques …will depend on the technology primitives and cost functions Penn ESE534 Spring2012 -- DeHon

Two’s Complement positive numbers in binary negative numbers subtract 1 and invert (or invert and add 1) Penn ESE534 Spring2012 -- DeHon

Two’s Complement 2 = 010 1 = 001 0 = 000 -1 = 111 -2 = 110 Penn ESE534 Spring2012 -- DeHon

Addition of Negative Numbers? …just works A: 111 B: 001 S: 000 A: 110 B: 001 S: 111 A: 111 B: 010 S: 001 A: 111 B: 110 S: 101 Penn ESE534 Spring2012 -- DeHon

Subtraction Negate the subtracted input and use adder which is: invert input and add 1 works for both positive and negative input 001  110 +1 = 111 111  000 +1 = 001 000  111 +1 = 000 010  101 +1 = 110 110  001 +1 = 010 Penn ESE534 Spring2012 -- DeHon

Subtraction (add/sub) Note: you can use the “unused” carry input at the LSB to perform the “add 1” Penn ESE534 Spring2012 -- DeHon

Overflow? A: 111 B: 001 S: 000 A: 110 B: 001 S: 111 A: 111 B: 010 Overflow=(A.s==B.s)*(A.s!=S.s) Penn ESE534 Spring2012 -- DeHon

Admin HW2 out today Reading for Wednesday online Penn ESE534 Spring2012 -- DeHon

Big Ideas [MSB Ideas] Can build arithmetic out of logic Penn ESE534 Spring2012 -- DeHon

Big Ideas [MSB-1 Ideas] Associativity Parallel Prefix Can perform addition in log time with linear area Penn ESE534 Spring2012 -- DeHon